-
公开(公告)号：US08990646B2
公开(公告)日：2015-03-24
申请号：US13485824
申请日：2012-05-31
CPC分类号： G11C29/44 , G06F11/2205 , G06F11/27 , G11C5/04 , G11C29/028 , G11C29/08 , G11C29/56008 , G11C29/76 , G11C2029/0401 , G11C2029/0409
摘要： An error test routine tests for a type of memory error by changing a content of a memory module. A memory handling procedure isolates the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure are to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.
摘要翻译： 错误测试例程通过更改内存模块的内容来测试内存错误类型。 存储器处理程序响应于错误测试例程的肯定结果来隔离存储器错误。 错误测试例程和内存处理过程将在运行时对操作系统透明执行。 存储与隔离存储器错误相对应的信息。
-
公开(公告)号：US20130326293A1
公开(公告)日：2013-12-05
申请号：US13485824
申请日：2012-05-31
CPC分类号： G11C29/44 , G06F11/2205 , G06F11/27 , G11C5/04 , G11C29/028 , G11C29/08 , G11C29/56008 , G11C29/76 , G11C2029/0401 , G11C2029/0409
摘要： An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.
摘要翻译： 错误测试例程是通过更改内存模块的内容来测试一种内存错误。 存储器处理过程是响应于错误测试例程的肯定结果来隔离存储器错误。 错误测试程序和内存处理程序将在运行时对操作系统透明执行。 存储与隔离存储器错误相对应的信息。
-
公开(公告)号：US08788904B2
公开(公告)日：2014-07-22
申请号：US13285742
申请日：2011-10-31
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： Example methods, apparatus, and articles of manufacture to perform error detection and correction are disclosed. A disclosed example method involves enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode. In addition, when the tagged memory mode is enabled in the memory controller, a five-error-correction-six-error-detection per-burst mode is selected to perform error correction on data. When the non-tagged memory mode is enabled in the memory controller, one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode is selected based on a pattern of error types in the data.
摘要翻译： 公开了用于执行错误检测和校正的示例性方法，装置和制造。 所公开的示例性方法涉及使存储器控制器能够以标记存储器模式或非标记存储器模式之一进行操作。 另外，当在存储器控制器中启用标记存储器模式时，选择五错误校正六错误检测每脉冲串模式以对数据执行纠错。 当在存储器控制器中启用非标记存储器模式时，每个突发模式的六错误校正七错误检测或单错误校正双错误检测每传输模式之一是 根据数据中的错误类型的模式进行选择。
-
公开(公告)号：US20120278651A1
公开(公告)日：2012-11-01
申请号：US13066976
申请日：2011-04-28
申请人： Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
发明人： Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
IPC分类号： G06F11/20
摘要： Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.
摘要翻译： 本文的实施例涉及用于重新映射数据的方法。 在一个实施例中，确定第一存储器块是否有故障。 指针被存储到第一存储器块，并且当第一存储器块发生故障时，设置第一存储器块的指针标志。 先前存储在第一存储器块的数据被写入第二存储器块，其中指针指向第二存储器块的位置。
-
公开(公告)号：US09411757B2
公开(公告)日：2016-08-09
申请号：US14005196
申请日：2011-03-14
申请人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
发明人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
IPC分类号： G06F13/16 , G06F13/362 , G06F13/38
CPC分类号： G06F13/3625 , G06F13/1605 , G06F13/1689
摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.
摘要翻译： 本公开提供了一种用于处理存储器存取操作的方法。 该方法包括至少部分地基于存储器模块的总存储器延迟来确定固定响应时间。 该方法还包括通过数据总线识别从存储器模块接收返回数据的可用时隙，其中当前时钟周期与可用时隙之间的时间差大于或等于固定响应时间。 该方法还包括通过预留可用时隙来创建第一时隙预留。 该方法还包括通过数据总线向存储器模块发出读取请求，其中读取请求以从第一时隙预留时间减去固定响应时间确定的时钟周期发出。
-
公开(公告)号：US09298621B2
公开(公告)日：2016-03-29
申请号：US13288996
申请日：2011-11-04
CPC分类号： G06F12/0813 , G06F9/5077 , G06F12/0817 , G06F12/10 , G06F12/1045 , G06F15/17381 , G06F2212/2542 , Y02D10/13 , Y02D10/22 , Y02D10/36
摘要： A chip multi-processor (CMP) with virtual domain management. The CMP has a plurality of tiles each including a core and a cache, a mapping storage, a plurality of memory controllers, a communication bus interconnecting the tiles and the memory controllers, and machine-executable instructions. The tiles and memory controllers are responsive to the instructions to group the tiles into a plurality of virtual domains, each virtual domain associated with at least one memory controller, and to store a mapping unique to each virtual domain in the mapping storage.
摘要翻译： 具有虚拟域管理的芯片多处理器（CMP）。 CMP具有多个瓦片，每个瓦片包括核心和高速缓存，映射存储器，多个存储器控制器，互连瓦片和存储器控制器的通信总线以及机器可执行指令。 瓦片和存储器控制器响应于将瓦片分组成多个虚拟域，与至少一个存储器控制器相关联的每个虚拟域以及存储映射存储器中的每个虚拟域唯一的映射的指令。
-
公开(公告)号：US20140208156A1
公开(公告)日：2014-07-24
申请号：US13387714
申请日：2011-01-27
申请人： Naveen Muralimanohar , Aniruddha Udipi , Chatterjee Niladrish , Balasubramonian Rajeev , Alan Lynn Davis , Norman Paul Jouppi
发明人： Naveen Muralimanohar , Aniruddha Udipi , Chatterjee Niladrish , Balasubramonian Rajeev , Alan Lynn Davis , Norman Paul Jouppi
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0673 , G06F11/1088 , G06F12/0802 , G06F12/0893 , G06F2212/1028 , G06F2212/3042 , G06F2212/305 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4082 , Y02D10/13
摘要： A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
摘要翻译： 所公开的示例性装置包括用于将对应于行（608）的行地址存储在存储器阵列（602）中的行地址寄存器（412）。 示例性装置还包括耦合到行地址寄存器的行解码器（604），用于在存储器接收列地址之后，在行的字线（704）上断言信号。 另外，示例性装置包括列解码器（606），用于基于列地址和在字线上断言的信号选择性地激活该行的一部分。
-
公开(公告)号：US20140040518A1
公开(公告)日：2014-02-06
申请号：US14005196
申请日：2011-03-14
申请人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
发明人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
IPC分类号： G06F13/362
CPC分类号： G06F13/3625 , G06F13/1605 , G06F13/1689
摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.
摘要翻译： 本公开提供了一种用于处理存储器存取操作的方法。 该方法包括至少部分地基于存储器模块的总存储器延迟来确定固定响应时间。 该方法还包括通过数据总线识别从存储器模块接收返回数据的可用时隙，其中当前时钟周期与可用时隙之间的时间差大于或等于固定响应时间。 该方法还包括通过预留可用时隙来创建第一时隙预留。 该方法还包括通过数据总线向存储器模块发出读取请求，其中读取请求以从第一时隙预留时间减去固定响应时间确定的时钟周期发出。
-
公开(公告)号：US20130111295A1
公开(公告)日：2013-05-02
申请号：US13285742
申请日：2011-10-31
CPC分类号： G06F11/1064
摘要： Example methods, apparatus, and articles of manufacture to perform error detection and correction are disclosed. A disclosed example method involves enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode. In addition, when the tagged memory mode is enabled in the memory controller, a five-error-correction-six-error-detection per-burst mode is selected to perform error correction on data. When the non-tagged memory mode is enabled in the memory controller, one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode is selected based on a pattern of error types in the data.
摘要翻译： 公开了用于执行错误检测和校正的示例性方法，装置和制造。 所公开的示例性方法涉及使存储器控制器能够以标记存储器模式或非标记存储器模式之一进行操作。 另外，当在存储器控制器中启用标记存储器模式时，选择五错误校正六错误检测每脉冲串模式以对数据执行纠错。 当在存储器控制器中启用非标记存储器模式时，每个突发模式的六错误校正七错误检测或单错误校正双错误检测每传输模式之一是 根据数据中的错误类型的模式进行选择。
-
公开(公告)号：US20120324156A1
公开(公告)日：2012-12-20
申请号：US13162946
申请日：2011-06-17
CPC分类号： G06F12/0246 , G06F3/0689 , G06F11/10 , G06F11/1008 , G06F11/1044 , G06F11/1076 , G06F11/108 , Y02D10/13
摘要： An exemplary embodiment of the present invention may build data blocks in non-volatile memory. The corresponding parity blocks may be built in a fast, high endurance memory.
摘要翻译： 本发明的示例性实施例可以在非易失性存储器中构建数据块。 相应的奇偶校验块可以内置在快速，高耐久性存储器中。
-
-
-
-
-
-
-
-
-
搜索结果
48 条记录 (耗时 0.018 秒)
