利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

59 条记录 (耗时 0.032 秒)

    LTR/OBFF DESIGN SCHEME FOR ETHERNET ADAPTER APPLICATION
    1.
    发明申请
    LTR/OBFF DESIGN SCHEME FOR ETHERNET ADAPTER APPLICATION 审中-公开
    用于以太网适配器的LTR / OBFF设计方案

    公开(公告)号：US20160162421A1

    公开(公告)日：2016-06-09

    申请号：US14907649

    申请日：2013-08-07

    申请人： Xuhong XIONG ,  Kevin ZHANG ,  Xiaofeng YAN ,  Jack DU ,  QUALCOMM INCORPORATED

    发明人： Xuhong Xiong ,  Kevin Zhang ,  Xiaofeng Yan ,  Jack Du

    IPC分类号： G06F13/20 ,  G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/20 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/3808 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method of reducing power consumption in a computing platform is disclosed. An endpoint-device that is coupled to the computing platform includes a first data buffer and a second data buffer. The first data buffer buffers outgoing data to be transmitted to an external device via a first communications medium. The second data buffer buffers incoming data received from the external device via the first communications medium. At least one of the first or second data buffers may selectively communicate with the computing platform, via a second communications medium, during an active window of the other data buffer. The active window may be requested by the first and/or second data buffers based, at least in part, on a system idle signal. For some embodiments, the first communications medium is an Ethernet link. Further, for some embodiments, the second communications medium is a Peripheral Component Interconnect Express (PCIe) link.

    摘要翻译： 公开了一种降低计算平台功耗的方法。 耦合到计算平台的端点设备包括第一数据缓冲器和第二数据缓冲器。 第一数据缓冲器缓冲经由第一通信介质发送到外部设备的输出数据。 第二数据缓冲器缓冲经由第一通信介质从外部设备接收的输入数据。 第一或第二数据缓冲器中的至少一个可以在另一数据缓冲器的活动窗口期间经由第二通信介质选择性地与计算平台通信。 至少部分地基于系统空闲信号，可以由第一和/或第二数据缓冲器请求活动窗口。 对于一些实施例，第一通信介质是以太网链路。 此外，对于一些实施例，第二通信介质是外围组件互连Express（PCIe）链路。

    Bitline floating during non-access mode for memory arrays
    2.
    发明授权
    Bitline floating during non-access mode for memory arrays 有权
    位线在内存阵列的非访问模式下浮动

    公开(公告)号：US08982659B2

    公开(公告)日：2015-03-17

    申请号：US12645623

    申请日：2009-12-23

    申请人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    发明人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang ,  Wei Chen

    IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C11/413

    CPC分类号： G11C7/12 ,  G11C5/141 ,  G11C11/413

    摘要： Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

    摘要翻译： 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

    Programmable read only memory
    5.
    发明申请
    Programmable read only memory 有权
    可编程只读存储器

    公开(公告)号：US20100046269A1

    公开(公告)日：2010-02-25

    申请号：US12229117

    申请日：2008-08-20

    申请人： Zhanping Chen ,  Sarvesh Kulkarni ,  Kevin Zhang

    发明人： Zhanping Chen ,  Sarvesh Kulkarni ,  Kevin Zhang

    IPC分类号： G11C17/00 ,  H01L21/82 ,  G11C11/34

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.

    摘要翻译： 公开了一组存储器单元。 存储单元包括熔丝和至少一个晶体管。 晶体管用于控制保险丝的编程或感测。 将编程电压施加到第一和第二导电层的堆叠。 堆叠的第一部分将编程电压耦合到单元中的晶体管的端子。 堆叠的第二部分将编程电压耦合到另一个单元中的晶体管的端子。

    Fuse cell having adjustable sensing margin
    6.
    发明授权
    Fuse cell having adjustable sensing margin 有权
    具有可调节传感距离的保险丝盒

    公开(公告)号：US07417913B2

    公开(公告)日：2008-08-26

    申请号：US11377135

    申请日：2006-03-15

    申请人： Zhanping Chen ,  Kevin Zhang

    发明人： Zhanping Chen ,  Kevin Zhang

    IPC分类号： G11C17/18

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： An apparatus, a method, and a system for fuse cells are disclosed herein. In various embodiments, a fuse cell may include circuitry to adjust a sensing margin. A fuse cell may include first and second fuse cells, and first and second resistance devices. The first resistance device may be configured to adjust a first voltage output from the first fuse cell, and the second resistance device may be configured to adjust a second voltage output from the second fuse cell. The first and second resistance devices may be configured adjust the first and second voltages asymmetrically.

    摘要翻译： 本文公开了一种用于熔丝电池的装置，方法和系统。 在各种实施例中，熔丝单元可以包括用于调整感测余量的电路。 熔丝单元可以包括第一和第二熔丝单元，以及第一和第二电阻装置。 第一电阻装置可以被配置为调整从第一熔丝单元输出的第一电压，并且第二电阻装置可以被配置为调整从第二熔丝单元输出的第二电压。 第一和第二电阻装置可以被配置为不对称地调节第一和第二电压。

    THIN FILM INTERLEAVER
    8.
    发明申请
    THIN FILM INTERLEAVER 有权
    薄膜交织器

    公开(公告)号：US20070223860A1

    公开(公告)日：2007-09-27

    申请号：US11753499

    申请日：2007-05-24

    申请人： Johnny Zhong ,  Yin Zhang ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

    发明人： Johnny Zhong ,  Yin Zhang ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

    IPC分类号： G02B6/26

    CPC分类号： G02B6/2937 ,  G02B6/29386 ,  H04J14/02

    摘要： A thin film interleaver device is disclosed. The thin film interleaver includes thin film optics. The thin film(s) are formed such that they reflect one group of wavelengths while allowing a second group of wavelengths to pass through the thin film(s). The thin film(s) exhibit a flat top frequency response across the channel bandwidths of the multiplexed signal for which the thin film filter is designed such that the thin film interleaver is less sensitive to wavelength drift and temperature variations.

    摘要翻译： 公开了一种薄膜交织器件。 薄膜交织器包括薄膜光学器件。 薄膜形成为使得它们反射一组波长，同时允许第二组波长穿过薄膜。 该薄膜在多路复用信号的通道带宽上表现出平坦的顶频响应，薄膜滤波器被设计成使得薄膜交织器对波长漂移和温度变化较不敏感。

    Cache leakage shut-off mechanism
    9.
    发明申请
    Cache leakage shut-off mechanism 有权
    缓存泄漏关闭机制

    公开(公告)号：US20070005999A1

    公开(公告)日：2007-01-04

    申请号：US11174204

    申请日：2005-06-30

    申请人： Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

    发明人： Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

    IPC分类号： G06F1/00

    CPC分类号： G06F1/32 ,  G06F1/3287 ,  G11C11/417 ,  Y02D10/171

    摘要： In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

    摘要翻译： 在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。 本文公开了其它实施例。 睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。 高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。 有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。

    Low insertion loss circulator
    10.
    发明申请
    Low insertion loss circulator 审中-公开
    低插入损耗循环器

    公开(公告)号：US20060044650A1

    公开(公告)日：2006-03-02

    申请号：US11196572

    申请日：2005-08-02

    申请人： Liren Du ,  Qi Deng ,  Kevin Zhang ,  Tengda Du

    发明人： Liren Du ,  Qi Deng ,  Kevin Zhang ,  Tengda Du

    IPC分类号： G02B27/28

    CPC分类号： G02F1/093 ,  G02B27/283

    摘要： This disclosure concerns low insertion loss optical circulators. In one example, the optical circulator has four ports and includes a polarization dividing and combining element that is positioned adjacent the first and fourth ports and is adapted to divide a beam of light into two beams of light of orthogonal polarizations. The polarization dividing and combining element is also adapted to combine two beams of light of orthogonal polarizations into one beam of light. The optical circulator also includes a Faraday rotator positioned near the second port, and a Faraday rotator positioned near the third port. The Faraday rotator rotates beams of light before or after the pass through the polarization dividing and combining elements.

    摘要翻译： 本公开涉及低插入损耗光学循环器。 在一个示例中，光循环器具有四个端口，并且包括位于第一和第四端口附近的偏振分割和组合元件，并且适于将光束分成两个正交偏振光束。 偏振分割和组合元件还适于将两个正交偏振光束组合成一个光束。 光循环器还包括位于第二端口附近的法拉第旋转器和位于第三端口附近的法拉第旋转器。 法拉第旋转器在通过偏振分割和组合元件之前或之后旋转光束。