公开(公告)号：US06422088B1

公开(公告)日：2002-07-23

申请号：US09666085

申请日：2000-09-21

申请人： Nobukazu Oba ,  Yoshifumi Murakami ,  Yukihiko Tanizawa ,  Hiroaki Tanaka ,  Seiichiro Ishio ,  Inao Toyoda ,  Yasutoshi Suzuki

发明人： Nobukazu Oba ,  Yoshifumi Murakami ,  Yukihiko Tanizawa ,  Hiroaki Tanaka ,  Seiichiro Ishio ,  Inao Toyoda ,  Yasutoshi Suzuki

IPC分类号： G01L900

CPC分类号： G01L27/007 ,  G01D3/08 ,  G01L9/0054 ,  G01L9/02 ,  G01R17/10

摘要： A reference voltage generating circuit is constituted by resistors RE and RF each having a resistance not influenced by an application of pressure. The reference voltage generating circuit is connected between one and the other ends of a bridge circuit. A failure judgement of the bridge circuit is performed based on a comparison of a voltage difference VBC between two midpoints B and C of the bridge circuit and voltage differences VCE and VBE between a reference voltage level of the reference voltage generating circuit and the voltage levels of two midpoints B and C.

摘要翻译： 参考电压发生电路由电阻器RE和RF构成，每个电阻器不受施加压力的影响。 参考电压产生电路连接在桥接电路的一端和另一端之间。 基于桥电路的两个中点B和C之间的电压差VBC与参考电压产生电路的参考电压电平之间的电压差VCE和VBE的比较，执行桥电路的故障判断， 两个中点B和C.

公开(公告)号：US06595065B2

公开(公告)日：2003-07-22

申请号：US09492605

申请日：2000-01-27

申请人： Yukihiko Tanizawa ,  Kazuaki Hamamoto ,  Inao Toyoda ,  Hiroaki Tanaka ,  Yasutoshi Suzuki

发明人： Yukihiko Tanizawa ,  Kazuaki Hamamoto ,  Inao Toyoda ,  Hiroaki Tanaka ,  Yasutoshi Suzuki

IPC分类号： G01L904

CPC分类号： G01L9/0055

摘要： A pressure detecting apparatus has a single-crystal semiconductor sensor chip disposed on a metallic diaphragm through a low melting point glass. The sensor chip has a planar shape selected from a circular shape, a first polygonal shape having more than five sides and having interior angles all less than 180°, and a second polygonal shape having a ratio of a circumscribed circle diameter relative to an inscribed circle diameter being less than 1.2. Four strain gauge resistors are disposed on X, Y axes passing through a center point O of the sensor chip in parallel with directions. Accordingly, thermal stress is reduced not to adversely affect a detection error and simultaneously high sensitivity is provided.

摘要翻译： 压力检测装置具有通过低熔点玻璃设置在金属隔膜上的单晶半导体传感器芯片。 传感器芯片具有选自圆形，多于五边的第一多边形和内角全部小于180°的平面形状，以及具有相对于内切圆的外接圆直径的比率的第二多边形 直径小于1.2。 四个应变计电阻器设置在X，Y轴上，与<110>方向平行地穿过传感器芯片的中心点O。 因此，热应力降低，不会不利地影响检测误差，同时提供高灵敏度。

公开(公告)号：US06194236B1

公开(公告)日：2001-02-27

申请号：US09247908

申请日：1999-02-11

申请人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Yukihiko Tanizawa ,  Koki Mizuno ,  Yasutoshi Suzuki ,  Yoshitsugu Abe ,  Hiroshi Tanaka ,  Motoki Ito ,  Kazuhisa Ikeda ,  Hiroshi Okada

发明人： Minekazu Sakai ,  Tsuyoshi Fukada ,  Yukihiko Tanizawa ,  Koki Mizuno ,  Yasutoshi Suzuki ,  Yoshitsugu Abe ,  Hiroshi Tanaka ,  Motoki Ito ,  Kazuhisa Ikeda ,  Hiroshi Okada

IPC分类号： H01L2166

CPC分类号： G01L9/0042 ,  H01L29/84 ,  Y10S438/977

摘要： An etching method for a silicon substrate, which can easily smooth the etching surface of the (110)-oriented silicon, is disclosed. A container is filled with KOH solution. In the KOH solution is immersed a (110)-oriented silicon wafer having a PN junction and is also disposed a platinum electrode plate to face the silicon wafer. To between a platinum electrode of the silicon wafer and the platinum electrode plate are connected a constant voltage power source, an ammeter and a contact in series. A controller starts etching from one surface on which the PN junction is formed, and terminates voltage application when the specified time lapses after the formation of an anodic oxide film is equilibrated with the etching of the anodic oxide film on the etching surface on the PN junction part. In this case, the controller detects flowing current through the ammeter, and the point of time when the equilibrium state is obtained is the point of inflection of the detected current to the constant current after the peak thereof.

摘要翻译： 公开了一种可以容易地平滑（110）取向的硅的蚀刻表面的硅衬底的蚀刻方法。 容器中充满KOH溶液。 在KOH溶液中浸渍具有PN结的（110）取向的硅晶片，并且还设置有与铂晶片相对的铂电极板。 在硅晶片的铂电极和铂电极板之间连接恒压电源，电流表和触点串联。 控制器从其上形成PN结的一个表面开始蚀刻，并且在阳极氧化膜形成之后指定的时间经过平衡后，在PN结的蚀刻表面上蚀刻阳极氧化膜来终止电压施加 部分。 在这种情况下，控制器检测通过电流表的流动电流，并且获得平衡状态的时间点是检测电流在其峰值之后的恒定电流的拐点。

公开(公告)号：US07834307B2

公开(公告)日：2010-11-16

申请号：US12010217

申请日：2008-01-22

申请人： Yukihiko Tanizawa

发明人： Yukihiko Tanizawa

IPC分类号： H01L31/00

CPC分类号： G01D5/246

摘要： A sensor circuit includes an analog-to-digital converter, a control circuit, a calculation circuit, and a pulse width modulation converter. The analog-to-digital converter converts an electric signal associated with a detected physical quantity to sensor data by sampling the electric signal a predetermined sampling number times per a predetermined sampling section. The control circuit determines the sampling number based on a magnitude of the electric signal. The calculation circuit calculates an average value of all the sensor data per the sampling section. The pulse width modulation converter generates a pulse width modulation signal having a pulse width corresponding to the average value.

摘要翻译： 传感器电路包括模数转换器，控制电路，计算电路和脉宽调制转换器。 模数转换器通过对每个预定采样部分的预定采样次数采样电信号，将与检测到的物理量相关联的电信号转换成传感器数据。 控制电路基于电信号的大小确定采样数。 计算电路计算每个采样部分的所有传感器数据的平均值。 脉冲宽度调制转换器产生具有对应于平均值的脉冲宽度的脉宽调制信号。

公开(公告)号：US20080309542A1

公开(公告)日：2008-12-18

申请号：US12153219

申请日：2008-05-15

申请人： Yukihiko Tanizawa

发明人： Yukihiko Tanizawa

IPC分类号： H03M1/40

CPC分类号： H03M1/089 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

摘要： An A/D converter circuit has a first ring delay line and a second ring delay line configured to vary respective characteristics in the same manner relative to a change in the ambient temperature. A reference voltage, which is free from a change in temperature, is fed as a power supply voltage to the second ring delay line. Digital data produced by the first ring delay line is temperature-compensated by digital data produced by the second ring delay line.

摘要翻译： A / D转换器电路具有第一环延迟线和第二环延迟线，其被配置为相对于环境温度的变化以相同的方式改变各自的特性。 没有温度变化的参考电压作为电源电压被馈送到第二环延迟线。 由第一环延迟线产生的数字数据由第二环延迟线产生的数字数据进行温度补偿。

公开(公告)号：US06861967B2

公开(公告)日：2005-03-01

申请号：US10893960

申请日：2004-07-20

申请人： Yukihiko Tanizawa

发明人： Yukihiko Tanizawa

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/60 ,  F03M1/06

CPC分类号： H03M1/1042 ,  H03M1/12

摘要： Predetermined reference voltages v1, v2 are A/D-converted to achieve corresponding digital data d0, d1, d2. Any reference digital values y1, y2 are set in advance so as to satisfy y1/y2=(v1−v0)/(v2−v0)=½. Furthermore, calculations of x1=d1−d0 and x2=d2−d0 are carried out to achieve x1, x2. A quadratic curve (quadratic function expression y=f(x)) passing a point D (x1, y1) and a point E (x2, y2) and the origin on the xy coordinate system is set as a linearly correcting expression. A shift value x achieved by subtracting d0 from data ds having non-linearity from the A/D converting circuit is corrected by the linearly correcting expression thus achieved to achieve a linearly corrected value y to ds.

摘要翻译： 预定参考电压v1，v2进行A / D转换，以实现对应的数字数据d0，d1，d2。 任何参考数字值y1，y2预先设定为满足y1 / y2 =（v1-v0）/（v2-v0）=½。 此外，执行x1 = d1-d0和x2 = d2-d0的计算以实现x1，x2。 通过点D（x1，y1）和点E（x2，y2）的二次曲线（二次函数表达式y = f（x））和xy坐标系上的原点被设置为线性校正表达式。 通过如此实现的线性校正表达式来校正通过从A / D转换电路的具有非线性的数据ds中减去d0而实现的移位值x，以实现线性校正值y至ds。

公开(公告)号：US20050017884A1

公开(公告)日：2005-01-27

申请号：US10893960

申请日：2004-07-20

申请人： Yukihiko Tanizawa

发明人： Yukihiko Tanizawa

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/60 ,  H03M1/06 ,  H03M1/62

CPC分类号： H03M1/1042 ,  H03M1/12

摘要： Predetermined reference voltages v1, v2 are A/D-converted to achieve corresponding digital data d0, d1, d2. Any reference digital values y1, y2 are set in advance so as to satisfy y1/y2=(v1−v0)/(v2−v0)=1/2. Furthermore, calculations of x1=d1−d0 and x2=d2−d0 are carried out to achieve x1, x2. A quadratic curve (quadratic function expression y=f(x)) passing a point D (x1, y1) and a point E (x2, y2) and the origin on the xy coordinate system is set as a linearly correcting expression. A shift value x achieved by subtracting d0from data ds having non-linearity from the A/D converting circuit is corrected by the linearly correcting expression thus achieved to achieve a linearly corrected value y to ds.

摘要翻译： 预定参考电压v1，v2进行A / D转换，以实现对应的数字数据d0，d1，d2。 任何参考数字值y1，y2预先设定为满足y1 / y2 =（v1-v0）/（v2-v0）= 1/2。 此外，执行x1 = d1-d0和x2 = d2-d0的计算以实现x1，x2。 通过点D（x1，y1）和点E（x2，y2）的二次曲线（二次函数表达式y = f（x））和xy坐标系上的原点被设置为线性校正表达式。 通过从由A / D转换电路得到的具有非线性的数据ds减去d0而获得的移位值x被这样实现的线性校正表达式来校正，以获得线性校正值y至ds。

公开(公告)号：US6064278A

公开(公告)日：2000-05-16

申请号：US181609

申请日：1998-10-28

申请人： Yukihiko Tanizawa

发明人： Yukihiko Tanizawa

IPC分类号： G01L9/00 ,  G01L9/06 ,  H03K7/08 ,  H03M1/48

CPC分类号： G01L9/06 ,  H03K7/08

摘要： A compact structure of a pulse-width modulator is provided which includes a clock generator, a counter, a D/A converter, a comparator, and a latching circuit. The clock generator generates clock signals. The counter counts the clock signals and provides a count signal indicative thereof in a digital form. The D/A converter converts the count signal into an analog signal. The comparator compares the analog signal converted by said D/A converter with an input signal to be pulse-width modulated to provide an output indicative thereof. The latching circuit latches the output of the comparator in response to a latch signal shifted from a change in level of the count signal to provide a pulse-width modulated signal.

摘要翻译： 提供了一种脉冲宽度调制器的紧凑结构，其包括时钟发生器，计数器，D / A转换器，比较器和锁存电路。 时钟发生器产生时钟信号。 计数器对时钟信号进行计数，并以数字形式提供指示其的计数信号。 D / A转换器将计数信号转换为模拟信号。 比较器将由D / A转换器转换的模拟信号与要进行脉宽调制的输入信号进行比较，以提供其指示的输出。 锁存电路响应于从计数信号的电平变化的锁存信号来锁存比较器的输出，以提供脉冲宽度调制信号。

公开(公告)号：US5525549A

公开(公告)日：1996-06-11

申请号：US49801

申请日：1993-04-21

申请人： Tsuyoshi Fukada ,  Yoshimi Yoshino ,  Yukihiko Tanizawa

发明人： Tsuyoshi Fukada ,  Yoshimi Yoshino ,  Yukihiko Tanizawa

IPC分类号： B81B3/00 ,  G01L9/00 ,  G01P15/08 ,  G01P15/12 ,  H01L21/3063 ,  H01L21/78 ,  H01L21/64

CPC分类号： B81C1/00888 ,  B81C1/00158 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/3063 ,  H01L21/78 ,  B81B2201/0235 ,  B81C2201/0114 ,  B81C2201/053 ,  Y10S148/028 ,  Y10S148/159 ,  Y10S438/977

摘要： A method for producing a semiconductor device that is capable of solving problems related to dicing a metal thin film used for electrochemical etching. According to the method, an n type epitaxial thin layer is formed on a p type single-crystal silicon wafer. An n.sup.+ type diffusion layer is formed in a scribe line area on the epitaxial layer. An n.sup.+ type diffusion layer is formed in an area of the epitaxial layer which corresponds to a predetermined portion of the wafer. An aluminum film is formed over the diffusion layers. The aluminum film has a clearance for passing a dicing blade. Portions of the wafer are electrochemically etched by supplying electricity through the aluminum film and the diffusion layers, to leave portions of the epitaxial layer. The wafer is diced into chips along the scribe line area. Each of the chips forms a separate semiconductor device. The electrochemical etching of the wafer is carried out after the formation of the aluminum film by immersing the wafer in a KOH aqueous solution and by supplying electricity through the aluminum film. The electrochemical etching is terminated at an inflection point where an etching current inflects to a constant level from a peak level. During the electrochemical etching, the diffusion layer reduces horizontal resistance in the epitaxial layer, so that the etched parts receive a sufficient potential to perform the etching.

摘要翻译： 一种能够解决与用于电化学蚀刻的金属薄膜切割相关的问题的半导体器件的制造方法。 根据该方法，在p型单晶硅晶片上形成n型外延薄层。 在外延层上的划线区域中形成n +型扩散层。 在对应于晶片的预定部分的外延层的区域中形成n +型扩散层。 在扩散层上形成铝膜。 铝膜具有用于通过切割刀片的间隙。 通过供电通过铝膜和扩散层对晶片的一部分进行电化学蚀刻，以留下外延层的部分。 晶片沿着划线区切成芯片。 每个芯片形成单独的半导体器件。 通过将晶片浸入KOH水溶液中并通过铝膜供电，在形成铝膜之后进行晶片的电化学蚀刻。 在蚀刻电流从峰值水平变为恒定水平的拐点处终止电化学蚀刻。 在电化学蚀刻期间，扩散层减小外延层中的水平电阻，使得蚀刻部分具有足够的电位进行蚀刻。

公开(公告)号：US08427352B2

公开(公告)日：2013-04-23

申请号：US13233272

申请日：2011-09-15

申请人： Yukihiko Tanizawa

发明人： Yukihiko Tanizawa

IPC分类号： H03M1/60

CPC分类号： H03M1/0621 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

摘要： An A/D converter circuit includes first to fourth pulse circulation circuits and first and second counters and configured to provide high conversion accuracy irrespective of a temperature change. The first pulse circulation circuit operates with a difference voltage of a specified voltage and an analog input voltage. The first counter outputs a difference of the number of pulse circulation in the first and the second pulse circulation circuits. The third pulse circulation circuit operates with a difference voltage of the specified voltage and a set voltage. The fourth pulse circulation circuit operates with the set voltage. The second counter outputs a difference of the number of pulse circulation in the third and the fourth pulse circulation circuits. When an output value of the second counter reaches a specified value, an output value of the first counter at that time is outputted as A/D conversion data.

摘要翻译： A / D转换器电路包括第一至第四脉冲循环电路和第一和第二计数器，并且被配置为提供与转换温度无关的高转换精度。 第一脉冲循环电路以指定电压和模拟输入电压的差分电压工作。 第一计数器输出第一和第二脉冲循环回路中脉冲循环次数的差。 第三脉冲循环电路以指定电压和设定电压的差分电压工作。 第四脉冲循环电路以设定电压工作。 第二计数器输出第三和第四脉冲循环回路中脉冲循环次数的差。 当第二计数器的输出值达到规定值时，将该时刻的第一计数器的输出值作为A / D转换数据输出。