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公开(公告)号：US5122869A
公开(公告)日：1992-06-16
申请号：US623827
申请日：1990-12-07
申请人： Norihide Kinugasa , Hikaru Masui , Yoshimitsu Saka , Koichi Yoshimura , Toshiaki Ioi , Narutoshi Kanazawa
发明人： Norihide Kinugasa , Hikaru Masui , Yoshimitsu Saka , Koichi Yoshimura , Toshiaki Ioi , Narutoshi Kanazawa
摘要： A video signal processing apparatus has a phase-locked loop which includes a quartz resonator, a voltage-controlled oscillator connected to the quartz resonator and oscillating at an oscillation frequency whose fundamental value is determined by the quartz resonator, and a horizontal sync signal lock circuit comparing a phase of a horizontal sync signal and a phase of an output signal from the voltage-controlled oscillator and controlling the oscillation frequency of the voltage-controlled oscillator in response to a difference between the phases of the horizontal sync signal and the output signal from the voltage-controlled oscillator. The video signal processing apparatus also has a device for modulating a video signal by use of the output signal from the voltage-controlled oscillator.
摘要翻译： 视频信号处理装置具有锁相环，该锁相环包括石英谐振器，连接到石英谐振器的压控振荡器，并以基波值由石英谐振器确定的振荡频率振荡;水平同步信号锁定电路 比较水平同步信号的相位和来自压控振荡器的输出信号的相位，并且响应于水平同步信号的相位和来自相应的输出信号之间的差异来控制压控振荡器的振荡频率 压控振荡器。 视频信号处理装置还具有通过使用来自压控振荡器的输出信号来调制视频信号的装置。
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2.发明授权Burst gate pulse generating device for use in image signal reproducing system 失效用于图像信号再现系统的突发脉冲产生装置
公开(公告)号：US5231509A
公开(公告)日：1993-07-27
申请号：US610192
申请日：1990-11-05
CPC分类号： H04N9/455
摘要： A signal processing apparatus for use in a video cassette recorder comprising a pilot burst gate pulse generating system means responsive to horizontal synchronizing signals successively generated in correspondance with horizontal scanning periods to process the horizontal synchronizing signals so as to produce pilot burst gate pulses. The pilot burst gate pulse generating system is responsive to a first horizontal synchronizing signal to generate the pilot burst gate pulse at a timing delayed by a predetemined time period from a leading edge of a second horizontal synchronizing signal following the first horizontal synchronizing signal. This arrangement allows stable generation of the pilot burst gate pulse at a timing slightly delayed from the active edge of the corresponding horizontal synchronizing signal.
摘要翻译： 一种在盒式磁带录像机中使用的信号处理装置，包括导频脉冲串脉冲发生系统装置，其响应于与水平扫描周期相应地连续产生的水平同步信号，以处理水平同步信号，以产生导频突发门脉冲。 导频突发门脉冲发生系统响应于第一水平同步信号，以在从第一水平同步信号之后的第二水平同步信号的前沿延迟预定时间周期的定时产生导频脉冲串门脉冲。 这种布置允许在相应的水平同步信号的有效边沿稍微延迟的定时稳定地产生导频突发门脉冲。
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3.发明申请SPIKE NOISE ELIMINATING CIRCUIT, DIGITAL SYSTEM USING THE SAME, AND IIC BUS 有权SPIKE噪声消除电路，使用它的数字系统和IIC总线公开(公告)号：US20100019838A1
公开(公告)日：2010-01-28
申请号：US12442649
申请日：2007-10-05
申请人： Norihide Kinugasa , Sachi Ota
发明人： Norihide Kinugasa , Sachi Ota
IPC分类号： H03K5/1252
CPC分类号： H03K5/1252
摘要： There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.
摘要翻译： 提供了一种尖峰噪声消除电路，其可以消除具有预定脉冲宽度或更小的可靠尖峰噪声，并且精确地发送和输出具有大于预定宽度的脉冲宽度的信号。 通过以下步骤来消除输入信号中的尖峰噪声：检测输入信号电平的一致性和通过将输入信号延迟最大待消除的噪声的脉冲宽度作为延迟量而获得的第一延迟信号; 并且基于作为检测到电平重合的结果获得的信号，对输入信号或通过将输入信号延迟一定时间段而获得的第二延迟信号进行采样。
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公开(公告)号：US07049867B2
公开(公告)日：2006-05-23
申请号：US10915340
申请日：2004-08-11
申请人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
发明人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/1803
摘要： A PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal is provided. The PLL circuit has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.
摘要翻译： 使得压控振荡器在短时间内收敛到稳定状态的PLL电路，并且即使在提供参考输入信号的周期期间发生不连续性，也产生具有高稳定性的时钟信号。 PLL电路具有压控振荡器，用于输出时钟控制，第一计数器由参考输入信号复位，该参考输入信号在用于输出第一信号的预定周期内比参考周期长一个周期;第二计数器，用于输出第二信号 ，用于复位第二计数器的复位脉冲发生电路，用于保持和输出由相位误差信号变化的控制电压的环路滤波器和用于检测在其周期之后最初输入的参考输入信号比参考值更长的不连续输入检测部分 期。
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公开(公告)号：US20050040872A1
公开(公告)日：2005-02-24
申请号：US10915340
申请日：2004-08-11
申请人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
发明人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
CPC分类号： H03L7/18 , H03L7/1803
摘要： The present invention provides a PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal. The PLL circuit of the present invention has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.
摘要翻译： 本发明提供一种使电压控制振荡器在短时间内收敛到稳定状态的PLL电路，即使在参考输入信号的周期中发生不连续性，也产生高稳定性的时钟信号。 本发明的PLL电路具有电压控制振荡器，用于输出时钟控制，第一计数器由参考输入信号复位，该参考输入信号在预定周期内具有比参考周期长一个周期，用于输出第一信号;第二计数器， 输出第二信号，用于复位第二计数器的复位脉冲发生电路，用于保持和输出由相位误差信号变化的控制电压的环路滤波器和用于检测在其周期之后最初输入的参考输入信号的不连续输入检测部分 比参考期长。
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公开(公告)号：US08325647B2
公开(公告)日：2012-12-04
申请号：US12750232
申请日：2010-03-30
CPC分类号： H04J3/047 , H04L7/0008
摘要： Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.
摘要翻译： n个信号转换检测部中的每一个检测与信号转变检测部对应的第一输入信号或第二输入信号中的至少一个的信号电平的转变。 当由n个信号转换检测部分中的至少一个检测到信号转换时，时分控制部分根据系统时钟输出控制脉冲。 n个输出切换部分中的每一个根据控制脉冲输出与输出切换部分相对应的第一或第二输入信号作为多路复用信号。
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公开(公告)号：US20080116983A1
公开(公告)日：2008-05-22
申请号：US11943227
申请日：2007-11-20
申请人： Norihide Kinugasa , Sachi Ota
发明人： Norihide Kinugasa , Sachi Ota
IPC分类号： H03L7/06
CPC分类号： H03L7/095
摘要： A PLL lock detection circuit produces a high precision PLL lock detection signal and enables eliminating a smoothing circuit. The PLL lock detection circuit reliably detects if the PLL circuit is locked reliably and without error by simultaneously evaluating both locked and unlocked states. A continuity detection unit detects if a PLL locked state continues for H consecutive periods, and another continuity detection unit detects if a PLL unlocked state continues for H consecutive periods. The continuity detection units simultaneously output the PLL locked/unlocked states, and an R-S latch holds the detection result.
摘要翻译： PLL锁定检测电路产生高精度PLL锁定检测信号，能够消除平滑电路。 PLL锁定检测电路通过同时评估锁定状态和解锁状态，可靠地检测PLL电路是否可靠且无错误地锁定。 连续性检测单元检测PLL锁定状态是否持续H个连续时段，另一个连续性检测单元检测PLL解锁状态是否持续H个连续时段。 连续性检测单元同时输出PLL锁定/解锁状态，R-S锁存器保持检测结果。
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公开(公告)号：US20050012531A1
公开(公告)日：2005-01-20
申请号：US10891230
申请日：2004-07-15
CPC分类号： H03K17/223
摘要： A power-on reset circuit of the present invention comprises: a first p-channel MOS transistor having the gate and the drain which are grounded and having a substrate which is connected to a power supply; a first resistor which is inserted and connected between the above-mentioned power supply and the source of the above-mentioned first p-channel MOS transistor; a first inverter having an input terminal which is connected to the source of the first p-channel MOS transistor; and a power-on reset signal output terminal which is connected to an output terminal of the first inverter.
摘要翻译： 本发明的上电复位电路包括：具有栅极和漏极的第一p沟道MOS晶体管，其接地并具有连接到电源的衬底; 插入并连接在上述电源和上述第一p沟道MOS晶体管的源极之间的第一电阻器; 第一反相器，具有连接到第一p沟道MOS晶体管的源极的输入端子; 以及连接到第一反相器的输出端子的上电复位信号输出端子。
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公开(公告)号：US06469647B1
公开(公告)日：2002-10-22
申请号：US09913519
申请日：2001-08-15
IPC分类号： H03M166
摘要： The digital-analog converter circuit includes: a high-order D-A converter circuit unit (100) for outputting a first voltage (Va) and a second voltage (Vb) both resulting from D-A conversion of the high-order five bits of a 13-bit input code to first and second output nodes (11, 12) through two buffers (10a, 10b) having the same characteristics, respectively; a low-order D-A converter circuit unit (200) for receiving the voltages on these two output nodes as reference voltages of an R-2R ladder circuit (201) and conducting D-A conversion of the low-order eight bits of the input code for output to a third output node (13); a sample-and-hold unit (250) for selectively sampling and holding the voltage on the third output node (13), i.e., the D-A conversion output of the 13-bit input code, according to a value of the input code; and an output unit (300) for multiplying the sampled and held D-A conversion output voltage by a gain with respect to an arbitrary central voltage. Thus, a D-A converter circuit capable of outputting a desired analog voltage with high accuracy even when a large number of bits are converted is implemented with a small chip area.
摘要翻译： 数模转换器电路包括：高阶DA转换器电路单元，用于输出由13位的高位五位的DA转换产生的第一电压（Va）和第二电压（Vb） 分别通过具有相同特征的两个缓冲器（10a，10b）将第一和第二输出节点（11,12）的位输入代码分配给第一和第二输出节点; 用于接收这两个输出节点上的电压作为R-2R梯形电路（201）的参考电压的低阶DA转换器电路单元（200），并且输入用于输出的输入代码的低8位的DA转换 到第三输出节点（13）; 采样保持单元，用于根据输入代码的值选择性地对第三输出节点（13）上的电压进行采样并保持13位输入代码的D-A转换输出; 以及用于将采样和保持的D-A转换输出电压相对于任意中心电压乘以增益的输出单元（300）。 因此，即使在大量位转换时也能以高精度输出期望的模拟电压的D-A转换器电路以小的芯片面积实现。
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公开(公告)号：US07916561B2
公开(公告)日：2011-03-29
申请号：US12332844
申请日：2008-12-11
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , H03D13/004 , H03L7/0812 , H03L7/0891
摘要： A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.
摘要翻译： 可变延迟电路连续地延迟输入时钟以产生具有不同相位的多个延迟时钟。 相位比较电路接收作为延迟时钟或输入时钟之一的第一参考时钟和作为延迟时钟之一并且其相位滞后于第一参考时钟之一的第二参考时钟，指定一个 并且根据第一参考时钟和第二参考时钟的电压电平仅在验证间隔期间比较第一和第二参考时钟的相位。 延迟控制电路根据由相位比较电路获得的比较结果控制可变延迟电路中的延迟时间。
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