公开(公告)号：US4939636A

公开(公告)日：1990-07-03

申请号：US15097

申请日：1987-02-17

申请人： Norio Nakagawa ,  Katsuaki Takagi ,  Tuneo Funabashi

发明人： Norio Nakagawa ,  Katsuaki Takagi ,  Tuneo Funabashi

IPC分类号： G06F15/16 ,  G06F12/02 ,  G06F15/177

CPC分类号： G06F12/0284

摘要： In a multiprocessor system having a hierachal memory device employing a virtual memory system, serial communication means which makes it possible for memory management units, which are disposed for CPUs, respectively, to communicate with one another, so that any change of common memory management information can be exchanged directly between the memory management units. As a result, it is not necessary for each CPU to inform the memory management unit of any change of the memory management information by an operating system, so that the overhead of communication between CPUs can be reduced and memory management can be made correctly without applying any load to the operating system even when any change occurs in the memory management information.

摘要翻译： 在具有采用虚拟存储器系统的层次存储器件的多处理器系统中，串行通信装置使得分别用于CPU的存储器管理单元可以彼此通信，使得公共存储器管理信息的任何改变 可以直接在内存管理单元之间交换。 结果，每个CPU不需要通过操作系统向存储器管理单元通知存储器管理信息的任何改变，从而可以减少CPU之间的通信开销，并且可以在不应用的情况下正确地进行存储器管理 即使在内存管理信息中发生任何更改，也可能对操作系统造成任何负载。

公开(公告)号：US4930104A

公开(公告)日：1990-05-29

申请号：US349402

申请日：1989-05-08

申请人： Norio Nakagawa ,  Katsuaki Takagi ,  Hirokazu Aoki

发明人： Norio Nakagawa ,  Katsuaki Takagi ,  Hirokazu Aoki

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04

摘要： A content-addressed memory which has a priority ranking circuit and/or a write control circuit provided in an output section thereof, the priority ranking circuit being adapted to be selectively operated so as to selectively output only one hit signal and the write control circuit being adapted to receive a hit signal and allow a corresponding memory cell to be brought into a write enable state.

公开(公告)号：US4831586A

公开(公告)日：1989-05-16

申请号：US909928

申请日：1986-09-22

申请人： Norio Nakagawa ,  Katsuaki Takagi ,  Hirokazu Aoki

发明人： Norio Nakagawa ,  Katsuaki Takagi ,  Hirokazu Aoki

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04

摘要： A content-addressed memory which has a priority ranking circuit and/or a write control circuit provided in an output section thereof, the priority ranking circuit being adapted to be selectively operated so as to selectively output only one hit signal and the write control circuit being adapted to receive a hit signal and allow a corresponding memory cell to be brought into a write enable state.

摘要翻译： 一种内容寻址存储器，其具有设置在其输出部分中的优先级排序电路和/或写控制电路，所述优先级排序电路适于选择性地操作以选择性地仅输出一个命中信号，并且所述写控制电路为 适于接收命中信号并允许对应的存储器单元进入写使能状态。

公开(公告)号：US5109491A

公开(公告)日：1992-04-28

申请号：US525550

申请日：1990-05-18

申请人： Norio Nakagawa ,  Katsuaki Takagi

发明人： Norio Nakagawa ,  Katsuaki Takagi

IPC分类号： G06F12/10 ,  G06F13/16 ,  G06F13/18 ,  G06F13/28 ,  G06F13/30

CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F13/285 ,  G06F13/30 ,  G06F12/1081

摘要： A memory management device which is connected in a virtual address space or a physical address space together with another device capable of becoming a bus master, is endowed with the function of detecting the bus request signal of the other device, interrupting an address translation process under execution and causing a processor to release a bus. Thus, the other device can be made the bus master without being kept waiting for a long time, and a system bug can be prevented which is attributed to such a fact that a wait time exceeds the data hold time of an input/output device connected to, for example, a direct memory access controller.

公开(公告)号：US4812969A

公开(公告)日：1989-03-14

申请号：US865840

申请日：1986-05-22

申请人： Katsuaki Takagi ,  Hirokazu Aoki ,  Norio Nakagawa ,  Yoshimune Hagiwara

发明人： Katsuaki Takagi ,  Hirokazu Aoki ,  Norio Nakagawa ,  Yoshimune Hagiwara

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F9/32 ,  G06F9/36

CPC分类号： G06F12/1036

摘要： An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit which, when a specific value is set in a common area field, invalidates comparison in a space number field.

摘要翻译： 在具有多虚拟空间的计算机系统中使用的地址转换单元包括全关联翻译后备缓冲器（TLB），其对于每个条目包括存储和比较地址的关联存储器阵列。 关联存储器阵列设置有当在公共区域字段中设置特定值时使空格号字段中的比较无效的电路。

公开(公告)号：US4653025A

公开(公告)日：1987-03-24

申请号：US685132

申请日：1984-12-21

申请人： Osamu Minato ,  Masakazu Aoki ,  Yuji Yatsuda ,  Katsuaki Takagi ,  Masashi Horiguchi

发明人： Osamu Minato ,  Masakazu Aoki ,  Yuji Yatsuda ,  Katsuaki Takagi ,  Masashi Horiguchi

IPC分类号： H01L27/00 ,  G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  G11C11/40

CPC分类号： G11C11/412

摘要： A static RAM having a plurality of memory cells. Each memory cell consists of driver MOST's that are connected to each other in a crossing manner, and transfer MOST's that connect storage nodes of the memory cell to the data lines. The driver MOST's are comprised of n-channel MOST's, and the transfer MOST's are comprised of p-channel MOST's.

摘要翻译： 具有多个存储单元的静态RAM。 每个存储器单元由以交叉方式彼此连接的驱动器MOST组成，并且传送将存储器单元的存储节点连接到数据线的MOST。 驱动器MOST由n沟道MOST组成，传输MOST由p沟道MOST组成。

公开(公告)号：US4577154A

公开(公告)日：1986-03-18

申请号：US517407

申请日：1983-07-26

申请人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

发明人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

IPC分类号： G01R22/00 ,  G01R21/127 ,  G06G7/161 ,  G06G7/186 ,  H03K7/06 ,  H03K7/08 ,  H03M1/50 ,  H03M1/82 ,  H03K5/05

CPC分类号： H03M1/82 ,  H03K7/08

摘要： A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above.The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

摘要翻译： 一种脉冲宽度调制电路，通过将简单的电路加到现有的脉宽调制电路上，可以消除三角波信号的偏移电压和比较器的偏移电压相对于时间的脉冲宽度调制的平均误差。 本发明还涉及使用上述脉冲宽度调制电路的两个模拟信号的乘积的积分电路。 本发明的原理结合了用于消除三角波信号的偏移的电路，通过在每个预定周期内相对于三角波信号相对于输入信号或输入信号反转三角波信号， 电路，用于通过反相比较器的输出来消除比较器的偏移，并且如果输入信号不被反相则替换比较器的输入端，或者如果输入信号反相则连接比较器的输入端。

公开(公告)号：US4562424A

公开(公告)日：1985-12-31

申请号：US517398

申请日：1983-07-26

申请人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Shuichi Torii ,  Kazuyoshi Ogawa

发明人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Shuichi Torii ,  Kazuyoshi Ogawa

IPC分类号： G01R22/00 ,  G01R21/00 ,  G01R21/127 ,  G01R21/133 ,  G06G7/186 ,  G01R21/06

CPC分类号： G01R21/133 ,  G01R21/00

摘要： An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input.The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

摘要翻译： 一种积分器电路，包括复位装置，当检测到输入模拟信号的积分器输出Vp与正或负参考值一致时，积分输出被复位到正和负参考值的中间附近 实际上不中断整合操作; 检测每次产生脉冲的电路; 以及产生指示由积分输入的增加或减少引起的一致性的方向信号的电路。 在方向信号指示增加的状态下产生的脉冲向上计数，并且在方向信号指示减小的状态下产生的脉冲向下计数，由此输入模拟信号的精确积分值 被检测。

公开(公告)号：US4388612A

公开(公告)日：1983-06-14

申请号：US287824

申请日：1981-07-28

申请人： Katsuaki Takagi ,  Yuzo Kita

发明人： Katsuaki Takagi ,  Yuzo Kita

IPC分类号： H03M1/66 ,  H03M1/00 ,  H03M1/38 ,  H03K13/02

CPC分类号： H03M1/38

摘要： An analog-to-digital converter includes a capacitor array circuit for determining m upper bits of a digital output, which includes a plurality of capacitors having binary-weighted capacitance ratios and a plurality of switches and which is connected to an input terminal of a sampled analog voltage and a reference voltage source. A resistor string circuit is provided for determining n lower bits of the digital output, including a plurality of switches and which is connected to the capacitor array circuit. A voltage comparator compares an output voltage of the capacitor array circuit with the ground potential and successive approximation registers successively provide pulses for controlling the switches of the capacitor array circuit and the resistor string circuit in accordance with the output of the voltage comparator. A circuit generates timing pulses for controlling the operation of the successive approximation registers. The resistor string circuit applies voltages equal to i/2.sup.n (where i denotes a value expressed by the n lower bits of the digital output) and (2.sup.n -i)/2.sup.n of a reference voltage to the capacitor array circuit, and the capacitor array circuit operates so as to put the input analog signal into a digital signal in accordance with a linear input/output conversion characteristic.

摘要翻译： 模数转换器包括用于确定数字输出的高位的电容器阵列电路，其包括具有二进制加权电容比的多个电容器和多个开关，并且连接到采样的输入端 模拟电压和参考电压源。 提供电阻串电路用于确定数字输出的n个较低位，包括多个开关，并连接到电容器阵列电路。 电压比较器将电容器阵列电路的输出电压与地电位进行比较，并且逐次逼近寄存器根据电压比较器的输出，依次提供用于控制电容器阵列电路和电阻串电路的开关的脉冲。 电路产生用于控制逐次逼近寄存器的操作的定时脉冲。 电阻串电路向电容器阵列电路施加等于i / 2n（其中i表示数字输出的n个较低位的值）和参考电压的（2n-i）/ 2n）的电压，并且电容器阵列 电路工作，以便根据线性输入/输出转换特性将输入模拟信号放入数字信号。

公开(公告)号：US5440708A

公开(公告)日：1995-08-08

申请号：US906967

申请日：1992-06-30

申请人： Katsuaki Takagi

发明人： Katsuaki Takagi

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F12/10 ,  G06F13/1668

摘要： A physical space management table is disposed outside the microprocessor in order to hold attribute data of the regions of the physical space held as a set of a plurality of regions in a manner corresponding to the regions of the physical space. The microprocessor is provided with a physical space management unit which fetches the attribute data from the physical space management table and manages them. The physical space management unit includes a physical space management table search control circuit, and a physical data buffer which primarily holds the attribute data obtained by the physical space management table search control circuit and the physical address in a manner corresponded to each other.

摘要翻译： 物理空间管理表被布置在微处理器的外部，以便以与物理空间的区域对应的方式来保存保持的多个区域的一组的物理空间的区域的属性数据。 微处理器设置有物理空间管理单元，其从物理空间管理表中提取属性数据并对其进行管理。 物理空间管理单元包括物理空间管理表搜索控制电路和主要保持由物理空间管理表搜索控制电路获得的属性数据和物理地址彼此对应的物理数据缓冲器。