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13 条记录 (耗时 0.023 秒)

    Circuit for integrating analog signal and converting it into digital signal
    1.
    发明授权
    Circuit for integrating analog signal and converting it into digital signal 失效
    用于集成模拟信号并将其转换为数字信号的电路

    公开(公告)号：US4562424A

    公开(公告)日：1985-12-31

    申请号：US517398

    申请日：1983-07-26

    申请人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Shuichi Torii ,  Kazuyoshi Ogawa

    发明人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Shuichi Torii ,  Kazuyoshi Ogawa

    IPC分类号： G01R22/00 ,  G01R21/00 ,  G01R21/127 ,  G01R21/133 ,  G06G7/186 ,  G01R21/06

    CPC分类号： G01R21/133 ,  G01R21/00

    摘要： An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input.The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

    摘要翻译： 一种积分器电路，包括复位装置，当检测到输入模拟信号的积分器输出Vp与正或负参考值一致时，积分输出被复位到正和负参考值的中间附近 实际上不中断整合操作; 检测每次产生脉冲的电路; 以及产生指示由积分输入的增加或减少引起的一致性的方向信号的电路。 在方向信号指示增加的状态下产生的脉冲向上计数，并且在方向信号指示减小的状态下产生的脉冲向下计数，由此输入模拟信号的精确积分值 被检测。

    Pulse width modulation circuit and integration circuit of analog product using said modulation circuit
    2.
    发明授权
    Pulse width modulation circuit and integration circuit of analog product using said modulation circuit 失效
    使用所述调制电路的模拟产品的脉宽调制电路和积分电路

    公开(公告)号：US4577154A

    公开(公告)日：1986-03-18

    申请号：US517407

    申请日：1983-07-26

    申请人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

    发明人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

    IPC分类号： G01R22/00 ,  G01R21/127 ,  G06G7/161 ,  G06G7/186 ,  H03K7/06 ,  H03K7/08 ,  H03M1/50 ,  H03M1/82 ,  H03K5/05

    CPC分类号： H03M1/82 ,  H03K7/08

    摘要： A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above.The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

    摘要翻译： 一种脉冲宽度调制电路，通过将简单的电路加到现有的脉宽调制电路上，可以消除三角波信号的偏移电压和比较器的偏移电压相对于时间的脉冲宽度调制的平均误差。 本发明还涉及使用上述脉冲宽度调制电路的两个模拟信号的乘积的积分电路。 本发明的原理结合了用于消除三角波信号的偏移的电路，通过在每个预定周期内相对于三角波信号相对于输入信号或输入信号反转三角波信号， 电路，用于通过反相比较器的输出来消除比较器的偏移，并且如果输入信号不被反相则替换比较器的输入端，或者如果输入信号反相则连接比较器的输入端。

    Electronic tuning type television receiver
    4.
    发明授权
    Electronic tuning type television receiver 失效
    电子调谐式电视接收机

    公开(公告)号：US4270220A

    公开(公告)日：1981-05-26

    申请号：US70817

    申请日：1979-08-29

    申请人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

    发明人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

    IPC分类号： H03J5/02 ,  H04B1/26

    CPC分类号： H03J5/0263

    摘要： A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diode.

    摘要翻译： 一种在其调谐电路的本地振荡器中采用可变电容二极管的电子调谐型电视接收机，其包括分别存储表示与多个通道对应的调谐电压的多个数字数据的存储器，使得对应于 所选择的通道可以应用于调谐电路中的可变电容二极管，D / A转换器将对应于所选通道的数字数据转换为要提供给可变电容二极管的模拟电压，以及调谐电压控制电路，其功能 以预定速率顺序地修改从存储器读出的所选通道的数字数据，直到在调谐电路中达到调谐点，并且将该信号顺序地施加到D / A转换器，由此调谐电路 可以调谐到所选择的频道，而不管v的操作特性的长期和其他变化 可调电容二极管。

    Memory driving method
    7.
    发明授权
    Memory driving method 失效
    内存驱动方式

    公开(公告)号：US4308596A

    公开(公告)日：1981-12-29

    申请号：US81890

    申请日：1979-10-04

    申请人： Atsushi Takai ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Terumi Sawase ,  Takaaki Hagiwara

    发明人： Atsushi Takai ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Terumi Sawase ,  Takaaki Hagiwara

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/40 ,  G11C13/00

    CPC分类号： G11C16/26 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10

    摘要： In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference V.sub.p exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference V.sub.p exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference V.sub.p exists between the substrate and the gate and when a potential difference V.sub.wd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage V.sub.wd between the source and drain and the substrate of the cell, applying a voltage V.sub.p between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.

    摘要翻译： 在每个具有至少栅极，衬底，源极和漏极的存储器单元的存储器阵列中，当衬底和源极和漏极处于相同的电位时，当存在电位差Vp时，进行写入操作 衬底和源极和漏极以及栅极处的电位。 当门和衬底之间存在电位差Vp时，存储的内容被擦除。 当存在基板和栅极之间的电位差Vp以及基板与源极和漏极之间存在电势差Vwd时，防止存储条件发生变化。 当这样的存储器阵列被部分地擦除时，通过在源极和漏极之间施加电压Vwd和电池的衬底之间施加电压V p来在单元的栅极和衬底之间施加电压V p来顺序地驱动不被擦除的单元， 对基板和电池栅极具有相同的电位。

    Signal converter
    8.
    发明授权
    Signal converter 失效
    信号转换器

    公开(公告)号：US4388612A

    公开(公告)日：1983-06-14

    申请号：US287824

    申请日：1981-07-28

    申请人： Katsuaki Takagi ,  Yuzo Kita

    发明人： Katsuaki Takagi ,  Yuzo Kita

    IPC分类号： H03M1/66 ,  H03M1/00 ,  H03M1/38 ,  H03K13/02

    CPC分类号： H03M1/38

    摘要： An analog-to-digital converter includes a capacitor array circuit for determining m upper bits of a digital output, which includes a plurality of capacitors having binary-weighted capacitance ratios and a plurality of switches and which is connected to an input terminal of a sampled analog voltage and a reference voltage source. A resistor string circuit is provided for determining n lower bits of the digital output, including a plurality of switches and which is connected to the capacitor array circuit. A voltage comparator compares an output voltage of the capacitor array circuit with the ground potential and successive approximation registers successively provide pulses for controlling the switches of the capacitor array circuit and the resistor string circuit in accordance with the output of the voltage comparator. A circuit generates timing pulses for controlling the operation of the successive approximation registers. The resistor string circuit applies voltages equal to i/2.sup.n (where i denotes a value expressed by the n lower bits of the digital output) and (2.sup.n -i)/2.sup.n of a reference voltage to the capacitor array circuit, and the capacitor array circuit operates so as to put the input analog signal into a digital signal in accordance with a linear input/output conversion characteristic.

    摘要翻译： 模数转换器包括用于确定数字输出的高位的电容器阵列电路，其包括具有二进制加权电容比的多个电容器和多个开关，并且连接到采样的输入端 模拟电压和参考电压源。 提供电阻串电路用于确定数字输出的n个较低位，包括多个开关，并连接到电容器阵列电路。 电压比较器将电容器阵列电路的输出电压与地电位进行比较，并且逐次逼近寄存器根据电压比较器的输出，依次提供用于控制电容器阵列电路和电阻串电路的开关的脉冲。 电路产生用于控制逐次逼近寄存器的操作的定时脉冲。 电阻串电路向电容器阵列电路施加等于i / 2n（其中i表示数字输出的n个较低位的值）和参考电压的（2n-i）/ 2n）的电压，并且电容器阵列 电路工作，以便根据线性输入/输出转换特性将输入模拟信号放入数字信号。

    Timing signal generating circuit
    9.
    发明授权
    Timing signal generating circuit 失效
    定时信号发生电路

    公开(公告)号：US4291241A

    公开(公告)日：1981-09-22

    申请号：US12708

    申请日：1979-02-16

    申请人： Koichi Mayama ,  Noboru Yamaguchi ,  Mamoru Sugie ,  Yuzo Kita ,  Shigeru Yoshizawa

    发明人： Koichi Mayama ,  Noboru Yamaguchi ,  Mamoru Sugie ,  Yuzo Kita ,  Shigeru Yoshizawa

    IPC分类号： H03K3/02 ,  G06F1/04 ,  G06F1/06 ,  G11C7/22 ,  G11C19/08 ,  H03K5/15

    CPC分类号： G11C7/22 ,  G06F1/04 ,  G11C19/08 ,  G11C19/0875 ,  H03K5/15066

    摘要： A timing signal generating circuit including a clock source which generates clock pulses of a predetermined period, a binary counter which divides the frequency of the clock pulses from the clock source by n, a logical array which decodes an output of the binary counter and which is composed of semiconductor elements and flip-flop circuits which are set or reset by outputs of the logical array in response to the clock pulses from the clock source with the outputs of the flip-flop circuits being used as timing signals.

    摘要翻译： 一种定时信号发生电路，包括产生预定周期的时钟脉冲的时钟源，将来自时钟源的时钟脉冲的频率除以n的二进制计数器，对二进制计数器的输出进行解码的逻辑阵列， 由半导体元件和触发器电路组成，其由响应于来自时钟源的时钟脉冲而由逻辑阵列的输出设置或复位，触发器电路的输出用作定时信号。