公开(公告)号：US12087893B2

公开(公告)日：2024-09-10

申请号：US17440213

申请日：2020-03-16

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Lutz Hoeppel ,  Attila Molnar

IPC: H01L33/60 ,  H01L33/00 ,  H01L33/22 ,  H01L33/62

CPC classification number: H01L33/62 ,  H01L33/0093 ,  H01L33/22 ,  H01L33/60 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: An optoelectronic semiconductor device may include a carrier having a roughened first main surface and optoelectronic semiconductor chips arranged over the roughened first main surface. The combined surface area of the optoelectronic semiconductor chips is smaller than the surface area of the carrier, and a part of the roughened first main surface is arranged between adjacent optoelectronic semiconductor chips.

公开(公告)号：US11367808B2

公开(公告)日：2022-06-21

申请号：US16216067

申请日：2018-12-11

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Fabian Kopp ,  Franz Eberhard ,  Björn Muermann ,  Attila Molnar

IPC: H01L33/38 ,  H01L33/24 ,  H01L33/46 ,  H01L33/20

Abstract: A radiation-emitting semiconductor chip includes a semiconductor body; a first contact layer having a first contact surface for external electrical contacting of the semiconductor chip and a first contact web structure connected to the first contact surface, wherein the first contact web structure is a region of the first contact layer that, compared to the first contact surface, has a comparatively small extent at least in a lateral direction; a second contact layer, wherein first and second contact web structures overlap in places in plan view of the semiconductor chip; a current distribution layer; and an insulation layer having a plurality of openings into which the current distribution layer extends.

公开(公告)号：US20190371969A1

公开(公告)日：2019-12-05

申请号：US16462483

申请日：2017-12-18

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Fabian Kopp ,  Attila Molnar

IPC: H01L33/38 ,  H01L33/46 ,  H01L33/14 ,  H01L33/40

Abstract: An optoelectronic semiconductor chip includes a contact layer that impresses current directly into a first semiconductor region present in direct contact with a current web, the first semiconductor region is an n-side and a second semiconductor region is a p-side of a semiconductor layer sequence, and a second mirror layer is applied directly to a second semiconductor region, a plurality of contact fields and isolator fields are arranged alternately along a longitudinal direction of the current web, in the contact fields, the contact layer is in direct contact with the current web, and the isolator fields are free of the contact layer, and a first mirror layer is located between the current web and the first semiconductor region.

公开(公告)号：US10446717B2

公开(公告)日：2019-10-15

申请号：US15573467

申请日：2016-05-09

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Fabian Kopp ,  Attila Molnar

IPC: H01L33/38 ,  H01L33/62 ,  H01L33/14 ,  H01L33/00 ,  H01L33/10

Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and an active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer, wherein the p-doped semiconductor layer is electrically contacted by a p-type connection contact, wherein a first trench extending at least partially into the p-doped semiconductor layer is arranged below the p-type connection contact, wherein an electrically insulating first blocking element arranged at least partially below the p-type connection contact and at least partially within the trench is arranged at least between the n-doped semiconductor layer and the p-type connection contact, and wherein the electrically insulating first blocking element is configured to prevent a direct current flow between the p-type connection contact and the p-doped and n-doped semiconductor layers and the active layer.

公开(公告)号：US10553755B2

公开(公告)日：2020-02-04

申请号：US15745940

申请日：2016-07-13

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Lutz Hoeppel ,  Attila Molnar

IPC: H01L33/22 ,  H01L33/00 ,  H01L33/38 ,  H01L33/44 ,  H01L33/32

Abstract: The invention relates, inter alia, to a method for producing a plurality of semiconductor chips, the method comprising the following steps: providing a substrate (1); applying a semiconductor layer sequence (2) to the substrate (1); generating a plurality of recesses (6) in the semiconductor layer sequence (2) on the side of the semiconductor layer sequence (2) that is facing away from the substrate (1); detaching the substrate (1) from the semiconductor layer sequence (2); thinning the semiconductor layer sequence (2) on the side that was facing the substrate (1) prior to detaching the substrate (1).

公开(公告)号：US20190103520A1

公开(公告)日：2019-04-04

申请号：US16085934

申请日：2017-03-16

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Fabian Kopp ,  Attila Molnar

IPC: H01L33/46 ,  H01L33/42 ,  H01L33/38

Abstract: A method for producing an optoelectronic semiconductor chip is specified, wherein a method step A) involves providing a semiconductor layer stack comprising a semiconductor layer of a first type, a semiconductor layer of a second type and an active layer arranged between the semiconductor layer of the first type and the semiconductor layer of the second type. Furthermore, the method comprises in a method step B) forming a mesa structure in the semiconductor layer of the first type, the semiconductor layer of the second type and the active layer. The method furthermore comprises in a method step C) applying a passivation layer to the mesa structure by means of vapour deposition or sputtering.

公开(公告)号：US11935989B2

公开(公告)日：2024-03-19

申请号：US17611189

申请日：2020-05-15

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Fabian Kopp ,  Attila Molnar ,  Roland Heinrich Enzmann

IPC: H01L33/38 ,  H01L31/0224 ,  H01L31/18 ,  H01L33/00 ,  H01L33/42

CPC classification number: H01L33/387 ,  H01L31/022408 ,  H01L31/1856 ,  H01L33/0062 ,  H01L33/42 ,  H01L2933/0016 ,  H01L2933/0066

Abstract: An optoelectronic semiconductor chip may include a first region doped with a first dopant, a second region doped with a second dopant, an active region between the first and second regions, a first contact layer having an electrically conductive material and covering the first region. An insulating layer may cover the first contact layer and include first openings, and the insulating layer may include a second contact layer having an electrically conductive material and covering the insulating layer and the first openings. The first openings may completely penetrate the insulating layer, and the second contact layer may include second openings and/or a third contact layer comprising an electrically conductive material is arranged in the first openings in each case between the second contact layer and the insulating layer.

公开(公告)号：US11107953B2

公开(公告)日：2021-08-31

申请号：US16607781

申请日：2018-05-16

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Attila Molnar

IPC: H01L33/38 ,  H01L33/62

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence having an active region arranged between first and second semiconductor layers; a first contact and a second contact for external electrical contacting of the semiconductor chip; first and second terminal layer regions, via which the first and second contacts electrically conductively connect to the first and second semiconductor layers; and a first insulation layer and a second insulation layer; wherein the first terminal layer region and the second terminal layer region are each arranged in some areas between the first insulation layer and the second insulation layer in a vertical direction perpendicular to a main extension plane of the active region; the first terminal layer region and the second terminal layer region are arranged side by side without overlapping; and the first terminal layer region extends in places up to a side surface of the semiconductor chip.

公开(公告)号：US20190341526A1

公开(公告)日：2019-11-07

申请号：US16462349

申请日：2017-12-12

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Fabian Kopp ,  Attila Molnar

IPC: H01L33/38 ,  H01L33/46 ,  H01L33/00

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence, a transparent substrate, at least one contact trench, at least one insulating trench, at least one current distribution trench, at least in the insulating trench, an electrically insulating mirror layer that reflects radiation generated in an active layer, at least one metallic current web in the contact trench configured for a current conduction along the contact trench and supplying current to a first semiconductor region, and at least one metallic busbar in the current distribution trench that energizes a second semiconductor region, wherein the contact trench, the isolating trench and the current distribution trench extend from a side of the second semiconductor region facing away from the substrate through the active layer into the first semiconductor region, and the contact trench is completely surrounded by the insulating trench, and the current distribution trench lies only outside the insulating trench.

公开(公告)号：US10381515B2

公开(公告)日：2019-08-13

申请号：US15939487

申请日：2018-03-29

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Fabian Kopp ,  Attila Molnar

IPC: H01L33/14 ,  H01L33/40 ,  H01L33/50 ,  H01L33/38 ,  H01L33/46 ,  H01L33/20 ,  H01L33/44

Abstract: An optoelectronic chip includes a semiconductor layer sequence including at least one n-doped semiconductor layer, at least one p-doped semiconductor layer, an active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer, wherein the p-doped semiconductor layer is electrically contacted by a p-connection contact, the n-doped semiconductor layer is electrically contacted by an n-connection contact, the semiconductor chip has at least two trenches, the p-connection contact is located within the first trench and the n-connection contact is located within the second trench, below the p-connection contact and within the first trench a first dielectric mirror element is arranged, which is electrically insulated, and below the n-connection contact and within the second trench and between the n-connection contact and the n-doped semiconductor layer, a second dielectric mirror element is arranged at least in regions, the second dielectric mirror element being electrically insulated.