公开(公告)号：US07169647B2

公开(公告)日：2007-01-30

申请号：US10842259

申请日：2004-05-07

申请人： Octavio Trovarelli ,  Ingo Uhlendorf ,  David Wallis ,  Axel Brintzinger

发明人： Octavio Trovarelli ,  Ingo Uhlendorf ,  David Wallis ,  Axel Brintzinger

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05016 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155

摘要： A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.

摘要翻译： 在半导体芯片和外部导体结构之间形成导电连接。 在半导体芯片的表面上施加高度元件，在升降元件上设置焊接岛。 在焊岛下方产生互连，只要接合岛或I / O焊盘即可。 可以通过防止焊料的流失和导电层的氧化或腐蚀来实现将接合岛或I / O焊盘与外部导电结构的导电连接的可靠性提高。

公开(公告)号：US20050275085A1

公开(公告)日：2005-12-15

申请号：US11140578

申请日：2005-05-27

申请人： Axel Brintzinger ,  Octavio Trovarelli ,  Ingo Uhlendorf ,  Stefan Ruckmich ,  David Wallis ,  Fritz Uhlendorf ,  Helga Uhlendorf

发明人： Axel Brintzinger ,  Octavio Trovarelli ,  Ingo Uhlendorf ,  Stefan Ruckmich ,  David Wallis ,  Fritz Uhlendorf ,  Helga Uhlendorf

IPC分类号： H01L23/12 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5222 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor (10) being respectively arranged between adjacent conductors of the redistribution routing (1) and/or at least a second passivation (7) with a lower dielectric constant of a preferred “cold dielectric” being arranged between the redistribution routing (1) and the first passivation (2) on the active region of the chip (3).

摘要翻译： 一种布置减少了芯片上的电串扰，特别是在再分配路由的相邻导体之间和/或芯片上的第一钝化上的再分配布线之间以及芯片的金属化之间的电串扰。 在一个方面，该布置减少了芯片上的再分配布线与其金属化之间的串扰，并且可以在前端简单且独立地实现。 这通过分别布置在再分配路由（1）的相邻导体和/或至少第二钝化层（7）之间的至少一个额外的导体（10）来实现，其中优选的“冷电介质”的较低介电常数被布置 在芯片（3）的有源区域上的再分配路由（1）和第一钝化（2）之间。

公开(公告)号：US07390742B2

公开(公告)日：2008-06-24

申请号：US11251594

申请日：2005-10-14

申请人： Axel Brintzinger ,  Stefan Ruckmich ,  Octavio Trovarelli ,  Fritz Uhlendorf, legal representative ,  David Wallis

发明人： Ingo Uhlendorf

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/4846 ,  H01L21/486 ,  H01L2924/0002 ,  H05K1/0287 ,  H05K1/0306 ,  H05K2201/09609 ,  Y10S438/976 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24917 ,  H01L2924/00

摘要： The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

摘要翻译： 本发明涉及一种用于生产具有在第一和第二表面之间具有通道连接的基底晶片的再布线印刷电路板的方法。 该方法的一个实施例包括在第一和第二表面上施加和图案化掩模层，从而揭露第一表面上的第一接触位置和第二表面上的第二接触位置; 在第二表面施加保护层，以便在随后的方法步骤期间保护相应的掩蔽层和第二接触位置; 将第一导体结构施加到第一表面，第一表面上的第一导体结构覆盖第一接触位置; 去除第二表面上的保护层; 以及将第二导体结构施加到所述第二表面，所述第二表面上的所述第二导体结构覆盖所述第二接触位置。

公开(公告)号：US07335591B2

公开(公告)日：2008-02-26

申请号：US10733217

申请日：2003-12-11

申请人： Axel Brintzinger ,  Ingo Uhlendorf

发明人： Axel Brintzinger ,  Ingo Uhlendorf

IPC分类号： H01L21/44

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method of forming a resist layer on a non-planar surface of a substrate includes placing the non-planar surface into an electrophoretic resist. While the non-planar surface is in the electrophoretic resist, an electrical voltage is applied between the substrate and the electrophoretic resist. The non-planar surface can then be removed from the electrophoretic resist.

摘要翻译： 在基板的非平面表面上形成抗蚀剂层的方法包括将非平面表面放置在电泳抗蚀剂中。 当非平面表面在电泳抗蚀剂中时，在基底和电泳抗蚀剂之间施加电压。 然后可以从电泳抗蚀剂去除非平面表面。

公开(公告)号：US06919264B2

公开(公告)日：2005-07-19

申请号：US10656042

申请日：2003-09-05

申请人： Axel Brintzinger ,  Ingo Uhlendorf ,  Andre Schenk ,  Alexander Wollanke

发明人： Axel Brintzinger ,  Ingo Uhlendorf ,  Andre Schenk ,  Alexander Wollanke

IPC分类号： H01L21/44 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/0401

摘要： A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.

摘要翻译： 提供了一种用于焊接停止构造晶片上的高度的方法，例如以弹性或柔性接触凸块的形式的3D接触结构，其通过金属化层电连接到晶片上的接合焊盘，金属化层延伸 由三维结构构成，由Au层覆盖的Cu / Ni层构成。 本发明提供了一种用于焊接停止构造晶片上的高程的方法，其可以简单可靠地实现以产生可靠的焊料停止和3D结构的良好的侧面保护。 根据本发明，抗蚀剂沉积在3D结构的尖端上，然后在包括抗蚀剂的金属化层上沉积阻焊层。 随后去除3D结构的尖端上的抗蚀剂，包括覆盖抗蚀剂的阻焊层，使得3D结构的尖端上的Au层被暴露。

公开(公告)号：US06409893B1

公开(公告)日：2002-06-25

申请号：US09606000

申请日：2000-06-29

申请人： Jurgen Holzbock ,  Olaf Knebel ,  Ingo Uhlendorf

发明人： Jurgen Holzbock ,  Olaf Knebel ,  Ingo Uhlendorf

IPC分类号： C25B900

CPC分类号： H01G9/2031 ,  H01G9/2009 ,  H01G9/2022 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/4226 ,  H01L51/441 ,  Y02E10/542 ,  Y02E10/549 ,  Y02P70/521

摘要： A photoelectrochemical cell, with a work electrode and a counter electrode that is arranged opposite the work electrode and whose electrochemically active surfaces are facing each other and with an electrolyte being arranged between the surfaces which contains a redox system, with the surface of the counter electrode being catalytically active, is characterized by the fact that the catalytically active surface of the counter electrode contains at least one polymer and/or at least one salt of a polymer, which has been doped to an intrinsically electrically conductive polymer through the redox system of the electrolyte.

摘要翻译： 一种光电化学电池，其具有与工作电极相对设置的工作电极和对电极，其电化学活性表面彼此相对，并且电解质被布置在包含氧化还原体系的表面之间，与对电极的表面 催化活性的特征在于，反电极的催化活性表面含有至少一种聚合物和/或至少一种聚合物的盐，该聚合物已经通过氧化还原体系掺杂到固有导电聚合物中 电解液

公开(公告)号：US07211504B2

公开(公告)日：2007-05-01

申请号：US10652520

申请日：2003-08-29

申请人： Ingo Uhlendorf

发明人： Ingo Uhlendorf

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05655 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014

摘要： A process is provided for the selective metallization of 3D structures, particularly for the selective gold-plating of 3D contact structures on wafers, such as contact bumps, which are electrically connected to a bond pad on the wafer via a three-dimensional, mechanically flexible structure in the form of a redistribution layer, for subsequent electrical connection to a carrier element, e.g., a printed circuit board. The process is intended to considerably simplify the process sequence. The metallization of the previously prepared 3D structures on the wafer is carried out electrochemically, under current or potential control, by the structures being partially immersed in an electrolyte with a fixed surface. The electrolyte can be covered with a membrane which is permeable to the corresponding ions, or alternatively a gel electrolyte may be used.

摘要翻译： 提供了一种用于3D结构的选择性金属化的方法，特别是用于在晶片上的3D接触结构的选择性镀金，例如接触凸块，其通过三维机械柔性电连接到晶片上的接合焊盘 结构以再分配层的形式，用于随后电连接到载体元件，例如印刷电路板。 该过程旨在大大简化过程顺序。 先前制备的3D结构在晶片上的金属化在电流或电位控制下通过部分浸入具有固定表面的电解质中的结构进行。 可以用对相应离子可渗透的膜覆盖电解质，或者也可以使用凝胶电解质。