公开(公告)号：US20140063744A1

公开(公告)日：2014-03-06

申请号：US13603905

申请日：2012-09-05

申请人： Osvaldo Jorge Lopez ,  Jonathan A. Noquil ,  Juan Alejandro Herbsommer

发明人： Osvaldo Jorge Lopez ,  Jonathan A. Noquil ,  Juan Alejandro Herbsommer

IPC分类号： H05K7/20 ,  H01L25/07 ,  H05K1/18

CPC分类号： H01L23/49575 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49537 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/074 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge (150c), the plate and extension spaced from the leadframe pad and the ridge connected to the pad; a vertically assembled stack of FET chips in the space between the plate and the pad, the stack including a first n-channel FET chip (120) having the drain terminal on one surface and the source and gate terminals on the opposite surface, the drain terminal attached to the pad, the source terminal attached to a second clip (140) tied to the first lead; and a second n-channel FET chip (130) having the source terminal on one surface and the drain and gate terminals on the opposite surface, the source terminal attached to the second clip, its drain terminal attached to the first clip; wherein the drain-source on-resistance of the FET stack is smaller than the on-resistance of the first FET chip and of the second FET chip.

摘要翻译： 一种功率FET（100），包括包括焊盘（110），第一引线（111）和第二引线（112）的引线框架; 包括板（150a），延伸部（150b）和脊（150c）的第一金属夹（150），所述板和延伸部与所述引线框垫间隔开并且连接到所述焊盘; 在板和焊盘之间的空间中垂直组装的FET芯片堆叠，所述堆叠包括在一个表面上具有漏极端子的第一n沟道FET芯片（120），并且在相对表面上具有源极和栅极端子，漏极 端子附接到焊盘，源极端子附接到与第一引线相连的第二夹子（140）; 以及第二n沟道FET芯片，其在一个表面上具有源极端子，在相对表面上具有漏极和栅极端子，源极端子附接到第二夹子，其漏极端子附接到第一夹子; 其中所述FET堆叠的所述漏极 - 源极导通电阻小于所述第一FET芯片和所述第二FET芯片的导通电阻。

公开(公告)号：US08049312B2

公开(公告)日：2011-11-01

申请号：US12352215

申请日：2009-01-12

申请人： Juan Alejandro Herbsommer ,  Jonathan A. Noquil ,  Osvaldo J. Lopez

发明人： Juan Alejandro Herbsommer ,  Jonathan A. Noquil ,  Osvaldo J. Lopez

IPC分类号： H01L23/495 ,  H01L23/10

CPC分类号： H01L23/4334 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012

摘要： A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.

摘要翻译： 半导体管芯封装包括：包括半导体管芯，附接到半导体管芯的上表面的夹结构和附接到夹结构的上表面的散热器的组件; 以及部分地封装所述组件的模制材料，其中所述散热器的上表面通过所述模制材料暴露。

公开(公告)号：US20100176508A1

公开(公告)日：2010-07-15

申请号：US12352215

申请日：2009-01-12

申请人： Juan Alejandro Herbsommer ,  Jonathan A. Noquil ,  Osvaldo J. Lopez

发明人： Juan Alejandro Herbsommer ,  Jonathan A. Noquil ,  Osvaldo J. Lopez

IPC分类号： H01L23/34 ,  H01L21/00

CPC分类号： H01L23/4334 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012

摘要： A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.

摘要翻译： 半导体管芯封装包括：包括半导体管芯，附接到半导体管芯的上表面的夹结构和附接到夹结构的上表面的散热器的组件; 以及部分地封装所述组件的模制材料，其中所述散热器的上表面通过所述模制材料暴露。

公开(公告)号：US20110008933A1

公开(公告)日：2011-01-13

申请号：US12836664

申请日：2010-07-15

申请人： Jonathan A. Noquil

发明人： Jonathan A. Noquil

IPC分类号： H01L21/60

CPC分类号： H01L23/49562 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/36 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

摘要翻译： 一种集成功率器件模块，包括具有第一和第二间隔衬垫的引线框架，位于第一和第二焊盘之间的一个或多个公共源极 - 漏极引线以及位于第二焊盘外侧的一个或多个漏极引线。 第一和第二晶体管分别与第一和第二焊盘连接，其中第二晶体管的源极电连接到一个或多个公共源极 - 漏极引线。 第一夹子附接到第一晶体管的漏极并电连接到一个或多个公共源极 - 漏极引线。 第二夹子连接到第二晶体管的漏极，并电连接到位于第二焊盘外侧的一个或多个漏极引线。 成型材料封装引线框架，晶体管和夹子以形成模块。

公开(公告)号：US07439613B2

公开(公告)日：2008-10-21

申请号：US10841656

申请日：2004-05-06

申请人： Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

发明人： Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC分类号： H01L21/44

CPC分类号： H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

摘要： A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.

摘要翻译： 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。 管芯附着表面和引线表面可以在不同的平面上。

公开(公告)号：US20070267728A1

公开(公告)日：2007-11-22

申请号：US11625100

申请日：2007-01-19

申请人： Jonathan A. Noquil ,  Yong Liu ,  Jocel Gomez

发明人： Jonathan A. Noquil ,  Yong Liu ,  Jocel Gomez

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/36 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board.

摘要翻译： 一种半导体封装组件，包括具有暴露的顶部发射极焊盘和暴露的底部源极焊盘的模制无引线封装（MLP）。 折叠的散热器通过软焊接附着工艺连接到MLP的暴露的顶部发射极焊盘。 折叠的散热器具有通常与MLP大体上共同延伸的平面构件，并且与MLP的顶部发射器焊盘电接触和热接触，并且还具有一个或多个垂直于平面构件的引线朝向下部的方向延伸 表面MLP。 这些散热器引线可以提供与印刷电路板（PC）板的发射极连接。

公开(公告)号：US20110003432A1

公开(公告)日：2011-01-06

申请号：US12882353

申请日：2010-09-15

申请人： Jonathan A. Noquil ,  Yong Liu ,  Jocel Gomez

发明人： Jonathan A. Noquil ,  Yong Liu ,  Jocel Gomez

IPC分类号： H01L21/60

CPC分类号： H01L23/3107 ,  H01L23/36 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board.

摘要翻译： 一种半导体封装组件，包括具有暴露的顶部发射极焊盘和暴露的底部源极焊盘的模制无引线封装（MLP）。 折叠的散热器通过软焊接附着工艺连接到MLP的暴露的顶部发射极焊盘。 折叠的散热器具有通常与MLP大体上共同延伸的平面构件，并且与MLP的顶部发射器焊盘电接触和热接触，并且还具有一个或多个垂直于平面构件的引线朝向下部的方向延伸 表面MLP。 这些散热器引线可以提供与印刷电路板（PC）板的发射极连接。

公开(公告)号：US07663211B2

公开(公告)日：2010-02-16

申请号：US11829793

申请日：2007-07-27

申请人： Jonathan A. Noquil ,  Ruben Madrid

发明人： Jonathan A. Noquil ,  Ruben Madrid

IPC分类号： H01L23/495 ,  H01L21/60 ,  H01L23/02 ,  H01L23/48

CPC分类号： H01L23/3107 ,  H01L23/36 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16245 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.

摘要翻译： 一种具有引线框结构的集成功率器件模块，其具有位于所述第一和第二焊盘之间的第一和第二间隔焊盘和一个或多个公共源极 - 漏极引线，分别附接到所述第一和第二焊盘的第一和第二晶体管倒装芯片， 的所述第二晶体管电连接到所述一个或多个公共源极 - 漏极引线，以及第一夹子，其附接到所述第一晶体管的漏极并电连接到所述一个或多个公共源极 - 漏极引线。 在另一个实施例中，部分封装的功率四边形扁平无引线封装具有暴露的顶部热漏夹，其基本上垂直于与折叠的柱头暴露的顶部热漏夹子的顶部热释放夹，以及暴露的热源垫。

公开(公告)号：US07492043B2

公开(公告)日：2009-02-17

申请号：US10927424

申请日：2004-08-26

申请人： Seung-yong Choi ,  Jonathan A. Noquil

发明人： Seung-yong Choi ,  Jonathan A. Noquil

IPC分类号： H01L23/34 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L25/072 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2224/05599

摘要： A power module flip chip package is provided. The power module flip chip package includes a package carrier having a front surface and a back surface facing the front surface, and a power semiconductor device electrically connected to the front surface of the package carrier via conductive bumps. The conductive bumps are electrically connected to a gate terminal, a source terminal, and a drain terminal of the power semiconductor device. The power module flip chip package has reduced resistance and inductance and improved reliability.

摘要翻译： 提供了电源模块倒装芯片封装。 电源模块倒装芯片封装包括具有面向前表面的前表面和后表面的封装载体，以及通过导电凸块电连接到封装载体的前表面的功率半导体器件。 导电凸块电连接到功率半导体器件的栅极端子，源极端子和漏极端子。 电源模块倒装芯片封装具有降低的电阻和电感并提高可靠性。

公开(公告)号：US07842555B2

公开(公告)日：2010-11-30

申请号：US12349140

申请日：2009-01-06

申请人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

发明人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC分类号： H01L21/60 ,  H01L21/98

CPC分类号： H01L23/562 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/97 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/00 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

摘要翻译： 集成晶体管模块包括限定至少一个低侧焊盘和至少一个高侧焊盘的引线框架。 引线框架的台阶部分将低边和高边平台机械地和电气地互连。 低侧晶体管安装在低侧焊盘上，其漏极电连接到低侧焊盘。 高侧晶体管安装在高侧焊盘上，其源极与高侧焊盘电连接。