-
1.发明授权公开(公告)号：US11536677B2
公开(公告)日：2022-12-27
申请号：US16471864
申请日：2017-12-18
Inventor： Ken Kawai , Koji Katayama , Shinichi Yoneda
IPC: G01N27/12 , B60L50/71 , G01N33/00 , H01L45/00 , H01M8/04082 , H01M8/0438 , B60K1/04 , B60K15/03 , G07C5/00
Abstract: A gas detection device includes a gas sensor and a drive circuit. The drive circuit includes a measurement circuit, a power supply circuit, and a control circuit. The gas sensor includes a first electrode, a second electrode, a metal-oxide layer disposed between the first electrode and the second electrode, and an insulating film that covers the first electrode, the second electrode, and the metal-oxide layer, and has an opening that exposes part of a main surface of the second electrode. A resistance value of the metal-oxide layer decreases when gas containing hydrogen atoms contact the second electrode. When the resistance value of the metal-oxide layer falls outside a predetermined range, the drive circuit applies a predetermined voltage between the first electrode and the second electrode to restore the resistance value of the metal-oxide layer back into the predetermined range.
-
公开(公告)号：US09524776B2
公开(公告)日：2016-12-20
申请号：US15130939
申请日：2016-04-16
Inventor： Ken Kawai , Koji Katayama
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2213/56
Abstract: A forming method includes: applying a first pulse voltage to a second electrode to a variable-resistance nonvolatile memory element in first state; and executing at least once a sequence that includes determining whether the variable-resistance nonvolatile memory element is in a second state, and continuously applying a second pulse voltage followed by a third pulse voltage to the variable-resistance nonvolatile memory element when the variable-resistance nonvolatile memory element is determined not to be in the second state.
Abstract translation: 一种形成方法包括：在第一状态下，向第二电极施加第一脉冲电压到可变电阻非易失性存储元件; 以及执行至少一次包括确定所述可变电阻非易失性存储元件是否处于第二状态的序列，并且当所述可变电阻器的可变电阻值为可变电阻时，向所述可变电阻非易失性存储器元件连续施加第二脉冲电压和第三脉冲电压 非易失性存储元件被确定为不处于第二状态。
-
Patent Agency Ranking
3.发明授权Variable resistance nonvolatile memory device including a variable resistance layer that changes reversibly between a low resistance state and a high resistance state according to an applied electrical signal 有权可变电阻非易失性存储装置包括根据所施加的电信号在低电阻状态和高电阻状态之间可逆地改变的可变电阻层公开(公告)号：US09336881B2
公开(公告)日：2016-05-10
申请号：US14730629
申请日：2015-06-04
Inventor： Kazuhiko Shimakawa , Ryotaro Azuma , Ken Kawai , Shunsaku Muraoka
CPC classification number: G11C13/0069 , G11C13/0007 , G11C2013/0071 , G11C2013/0073 , G11C2013/009 , G11C2213/79 , G11C2213/82
Abstract: A variable resistance nonvolatile memory device includes: a nonvolatile memory element; an NMOS transistor connected to the nonvolatile memory element; a source line connected to the NMOS transistor; a bit line connected to the nonvolatile memory element. When a control circuit causes the nonvolatile memory element to be in the low resistance state, the control circuit controls to flow a first current from a first voltage source to a reference potential point, and applies a first gate voltage to a gate of a NMOS transistor, and when the control circuit causes the nonvolatile memory element to be in the high resistance state, the control circuit controls to flow a second current from a second voltage source to the reference potential point, and applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage.
Abstract translation: 一种可变电阻非易失性存储器件包括：非易失性存储元件; 连接到非易失性存储元件的NMOS晶体管; 连接到NMOS晶体管的源极线; 连接到非易失性存储元件的位线。 当控制电路使非易失性存储元件处于低电阻状态时，控制电路控制第一电流从第一电压源流向基准电位点，并将第一栅极电压施加到NMOS晶体管的栅极 并且当控制电路使非易失性存储元件处于高电阻状态时，控制电路控制将第二电流从第二电压源流向基准电位点，并将第二栅极电压施加到栅极 NMOS晶体管，第二栅极电压低于第一栅极电压。
-
4.发明授权Write method for writing to variable resistance nonvolatile memory element and variable resistance nonvolatile memory device 有权写入可变电阻非易失性存储器元件和可变电阻非易失性存储器件的写入方法公开(公告)号：US09202565B2
公开(公告)日：2015-12-01
申请号：US14118635
申请日：2013-03-13
Inventor： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0007 , G11C13/0011 , G11C13/0033 , G11C13/0097 , G11C2013/0092 , G11C2213/55
Abstract: A write method for writing to a variable resistance nonvolatile memory element, comprising applying a set of strong recovery-voltage pulses at least once to the variable resistance nonvolatile memory element when it is determined that the resistance state of the variable resistance nonvolatile memory element fails to change to a second resistance state, remaining in a first resistance state, the set of strong recovery-voltage pulses including pulses: (1) a first strong recovery-voltage pulse which has a greater amplitude than a normal second voltage for changing the resistance state to the first resistance state, and has the same polarity as the second voltage; and (2) a second strong recovery-voltage pulse which follows the first strong recovery-voltage pulse and has a longer pulse width than the pulse width of the normal first voltage for changing the resistance state to the second resistance state, and has the same polarity as the first voltage.
Abstract translation: 一种用于写入可变电阻非易失性存储元件的写入方法，包括当确定可变电阻非易失性存储元件的电阻状态不能够时，将至少一次的一组强恢复电压脉冲施加到可变电阻非易失性存储元件 改变为第二电阻状态，保持在第一电阻状态，包括脉冲的强恢复电压脉冲集合：（1）具有比用于改变电阻状态的正常第二电压更大的幅度的第一强恢复电压脉冲 并具有与第二电压相同的极性; 和（2）第二强恢复电压脉冲，其跟随第一强恢复电压脉冲并且具有比用于将电阻状态改变为第二电阻状态的正常第一电压的脉冲宽度更长的脉冲宽度，并且具有相同 极性作为第一电压。
-
5.发明授权Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device 有权可变电阻非易失性存储元件写入方法和可变电阻非易失性存储器件公开(公告)号：US09001557B2
公开(公告)日：2015-04-07
申请号：US13990209
申请日：2012-11-21
Inventor： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
CPC classification number: G11C13/0069 , G11C13/00 , G11C13/004 , G11C13/0064 , G11C2013/0073 , G11C2013/0092
Abstract: Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.
Abstract translation: 提供一种写入能够改善保持特性和扩大操作窗口的可变电阻非易失性存储元件的方法。 在写入方法中，为了写入“1”数据（LR），首先执行将用于将可变电阻非易失性存储元件变更为中间电阻状态而设定的弱的HR写入电压脉冲的弱的HR写入处理， 随后，执行LR写入处理，其中设置用于将可变电阻非易失性存储元件从中间电阻状态改变为LR状态的LR写入电压脉冲。
-
6.发明授权公开(公告)号：US09484090B2
公开(公告)日：2016-11-01
申请号：US14635297
申请日：2015-03-02
Inventor： Yuhei Yoshimoto , Kazuhiko Shimakawa , Ken Kawai , Ryotaro Azuma
CPC classification number: G11C13/004 , G11C7/062 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0061 , G11C13/0069 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/70 , G11C2013/005 , G11C2013/0054 , G11C2013/0073 , G11C2013/009 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146
Abstract: A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the selected memory cell are provided. In memory cells of odd-numbered-layer and even-numbered-layer memory cell arrays that constitute a multilayer memory cell array, each memory cell in any of the layers has a selection element, a first electrode, a first resistance change layer, a second resistance change layer, and a second electrode that are disposed in the same order. Whether the selected memory cell is located in any layer of the multilayer memory cell array, the read circuit applies a voltage to the selected memory cell to perform the reading operation. The voltage applied to the selected memory cell causes the second electrode to become positive with reference to the first electrode in the selected memory cell.
Abstract translation: 提供从存储单元阵列选择存储单元的选择电路和用于读取所选存储单元中的电阻变化元件的电阻状态的读取电路。 在构成多层存储单元阵列的奇数层和偶数层存储单元阵列的存储单元中，任何层中的每个存储单元都具有选择元件，第一电极，第一电阻改变层， 第二电阻变化层和第二电极。 所选择的存储单元是否位于多层存储单元阵列的任何层中，读取电路向所选存储单元施加电压以执行读取操作。 施加到所选择的存储单元的电压使得第二电极参照所选择的存储单元中的第一电极变为正。
-
公开(公告)号：US11027604B2
公开(公告)日：2021-06-08
申请号：US16468558
申请日：2017-12-08
Inventor： Ken Kawai , Shinichi Yoneda
Abstract: A hydrogen detection apparatus includes a hydrogen sensor, a sensor control circuit configured to sense a resistance value of the hydrogen sensor, and a microcomputer configured to set an off time that differs depending on an operating environment and intermittently drive the sensor control circuit. The hydrogen sensor includes a first electrode; a metal-oxide layer on the first electrode, and in which a resistance value is configured to change in response to contacting hydrogen atoms; a second electrode on the metal-oxide layer; and an insulating film that covers at least a portion of lateral surfaces of the first electrode, the metal-oxide layer, and the second electrode. A portion of at least one of: (i) a first interface between the first electrode and the metal-oxide layer; and (ii) a second interface between the second electrode and the metal-oxide layer is uncovered by the insulating film and exposed to a detection space.
-
-
-
-
-
-
Search Results
7
records
(took 0.019 seconds)
