公开(公告)号：US09064570B2

公开(公告)日：2015-06-23

申请号：US13985435

申请日：2012-12-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshio Kawashima ,  Yukio Hayakawa

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0064 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/56 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

Abstract translation: 非易失性存储器件包括：存储单元阵列，包括多个存储单元，每个存储单元包括可变电阻元件和第一电流控制元件; 和当前的导向元件参数产生电路。 当前的导向元件参数产生电路包括：放置在基板和第二层间电介质之间的第三线; 位于第二层间电介质上方的第四线; 以及当在第三线和第四线之间移除可变电阻元件时，连接在第三线和第四线之间的第二电流导向元件，而不存在可变电阻元件，并具有相同的非线性电流转向特性 作为第一当前的转向元件。

公开(公告)号：US09054305B2

公开(公告)日：2015-06-09

申请号：US14207763

申请日：2014-03-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Satoru Ito ,  Yoshio Kawashima ,  Yukio Hayakawa ,  Takumi Mikawa

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/22

CPC classification number: H01L45/1253 ,  H01L27/222 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements.

Abstract translation: 非易失性存储器件包括多个非易失性存储元件，每个非易失性存储元件具有上电极，可变电阻层和下电极; 嵌入所述多个非易失性存储元件的第一绝缘层，并且在所述非易失性存储元件的每一个中，从所述下电极的最下部分到高于所述上电极的最上部的位置; 第二绝缘层，形成在第一绝缘层上，并且具有比第一绝缘层中包含的空位的平均尺寸大的空位的平均尺寸，或平均碳浓度高于第一绝缘层的平均碳浓度 ; 以及贯穿所述第二绝缘层和所述第一绝缘层的一部分并且连接到包括在所述非易失性存储元件中的至少一个上电极的导电层。

公开(公告)号：US09444044B2

公开(公告)日：2016-09-13

申请号：US14642957

申请日：2015-03-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yukio Hayakawa ,  Yoshio Kawashima

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A resistive nonvolatile storage device includes a first interlayer insulating layer provided above a substrate, a contact hole penetrating through the first interlayer insulating layer, a contact layer wholly covering a bottom surface and a sidewall surface of the contact hole and extending to at least partially cover an upper surface of the first interlayer insulating layer, a contact plug filled in the contact hole, an upper surface of the contact plug being positioned below an upper surface of the contact layer, a lower electrode provided on both the contact plug and the contact layer that is provided on the part of the upper surface of the first interlayer insulating layer, and a resistance change layer provided on the lower electrode, and an upper electrode that is provided on the resistance change layer.

Abstract translation: 电阻性非易失性存储装置包括设置在基板上方的第一层间绝缘层，穿过第一层间绝缘层的接触孔，完全覆盖底表面的接触层和接触孔的侧壁表面，并延伸至至少部分覆盖 所述第一层间绝缘层的上表面，填充在所述接触孔中的接触塞，所述接触插塞的上表面位于所述接触层的上表面的下方，设置在所述接触插塞和所述接触层两者上的下电极 设置在第一层间绝缘层的上表面的一部分上，以及设置在下电极上的电阻变化层，以及设置在电阻变化层上的上电极。

公开(公告)号：US09478584B2

公开(公告)日：2016-10-25

申请号：US14559914

申请日：2014-12-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshio Kawashima ,  Yukio Hayakawa ,  Atsushi Himeno

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: A nonvolatile memory device includes an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs, each of the plurality of the contact plugs penetrating through each of the plurality of the oxygen diffusion prevention layers and at least a part of the insulating layer, and a plurality of resistance-variable elements, each of the plurality of the resistance-variable elements covering each of the plurality of the contact plugs exposed on surfaces of the oxygen diffusion prevention layers and being electrically connected to each of the plurality of the contact plugs Each of the oxygen diffusion prevention layers is provided only between the insulating layer and each of the plurality of the resistance-variable elements to correspond to each of the plurality of the contact plugs arranged for each of the plurality of the resistance-variable elements.

Abstract translation: 非易失性存储器件包括绝缘层，设置在绝缘层上的氧扩散防止层，多个接触插塞，多个接触插塞中的每一个穿透多个氧扩散防止层中的每一个，以及至少一部分 和多个电阻可变元件，所述多个电阻可变元件中的每一个覆盖在所述氧扩散防止层的表面上暴露的所述多个所述接触插塞中的每一个，并且电连接到所述绝缘层 多个接触插塞每个氧扩散防止层仅设置在绝缘层和多个电阻可变元件中的每一个之间，以对应于为多个电阻中的每一个布置的多个接触插塞中的每一个 可变元素

公开(公告)号：US10923560B2

公开(公告)日：2021-02-16

申请号：US16259102

申请日：2019-01-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takahiro Koyanagi ,  Yuuko Tomekawa ,  Takeshi Harada ,  Yoshio Kawashima

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/3215 ,  H01L21/285 ,  H01L21/02 ,  H01L27/146 ,  H01L27/108

Abstract: A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode and which is in contact with the first electrode. The first electrode includes a first portion including an interface between the first electrode and the dielectric layer, the dielectric layer includes a second portion including the interface, and the first portion and the second portion each contain silicon. A concentration distribution of the silicon along a thickness direction of the first portion and the second portion includes a convex portion intersecting the interface.