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公开(公告)号：US20140032815A1
公开(公告)日：2014-01-30
申请号：US13559319
申请日：2012-07-26
申请人： Paolo E. Mangalindan , Alberto Troia , Yihua Zhang , Poorna Kale
发明人： Paolo E. Mangalindan , Alberto Troia , Yihua Zhang , Poorna Kale
CPC分类号： G11C16/00 , G06F1/12 , G06F1/324 , G06F13/1689 , G06F13/4243 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C29/023 , G11C2207/2254 , H04L1/24 , H04L7/10 , H04L2001/0094
摘要： Methods and apparatuses for calibrating data sampling points are disclosed herein. An example apparatus may include a memory that may be configured to receive a calibration command and an attribute. The memory may include a first register that is configured to store a tuning data pattern and a second register that is configured to receive and store the tuning data pattern stored in the first register. The second register may be further configured to store the tuning data pattern responsive, at least in part, to the memory receiving the calibration command. The memory may be configured to execute an operation on at least one of the tuning data pattern stored in the first register or the tuning data pattern stored in the second register based, at least in part, on the attribute.
摘要翻译： 本文公开了用于校准数据采样点的方法和装置。 示例性装置可以包括可被配置为接收校准命令和属性的存储器。 存储器可以包括被配置为存储调谐数据模式的第一寄存器和被配置为接收和存储存储在第一寄存器中的调谐数据模式的第二寄存器。 第二寄存器还可以被配置为至少部分地响应于存储器接收校准命令来存储调谐数据模式。 存储器可以被配置为至少部分地基于该属性来对存储在第一寄存器中的调谐数据模式或存储在第二寄存器中的调谐数据模式中的至少一个执行操作。
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公开(公告)号：US09214232B2
公开(公告)日：2015-12-15
申请号：US13559319
申请日：2012-07-26
申请人： Paolo E. Mangalindan , Alberto Troia , Yihua Zhang , Poorna Kale
发明人： Paolo E. Mangalindan , Alberto Troia , Yihua Zhang , Poorna Kale
IPC分类号： G06F12/00 , G11C16/00 , G06F13/16 , H04L1/24 , G06F13/42 , G11C7/22 , G11C11/4076 , G11C29/02 , G06F1/12 , G06F1/32 , H04L7/10
CPC分类号： G11C16/00 , G06F1/12 , G06F1/324 , G06F13/1689 , G06F13/4243 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C29/023 , G11C2207/2254 , H04L1/24 , H04L7/10 , H04L2001/0094
摘要： Methods and apparatuses for calibrating data sampling points are disclosed herein. An example apparatus may include a memory that may be configured to receive a calibration command and an attribute. The memory may include a first register that is configured to store a tuning data pattern and a second register that is configured to receive and store the tuning data pattern stored in the first register. The second register may be further configured to store the tuning data pattern responsive, at least in part, to the memory receiving the calibration command. The memory may be configured to execute an operation on at least one of the tuning data pattern stored in the first register or the tuning data pattern stored in the second register based, at least in part, on the attribute.
摘要翻译： 本文公开了用于校准数据采样点的方法和装置。 示例性装置可以包括可被配置为接收校准命令和属性的存储器。 存储器可以包括被配置为存储调谐数据模式的第一寄存器和被配置为接收和存储存储在第一寄存器中的调谐数据模式的第二寄存器。 第二寄存器还可以被配置为至少部分地响应于存储器接收校准命令来存储调谐数据模式。 存储器可以被配置为至少部分地基于该属性来对存储在第一寄存器中的调谐数据模式或存储在第二寄存器中的调谐数据模式中的至少一个执行操作。
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公开(公告)号：US20130332789A1
公开(公告)日：2013-12-12
申请号：US13490690
申请日：2012-06-07
申请人： Alberto Troia
发明人： Alberto Troia
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0688 , G06F11/1048 , G11C16/26 , G11C29/52 , H03M13/13
摘要： A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An external controller generates error correction data in response to associated data to be transmitted. The error correction data is divided into multiple data packets and appended to the corresponding data for transmission over the data bus. The memory device can use the ECC data, if the feature is enabled, to attempt to correct the corresponding data and store both the corrected data and the ECC data.
摘要翻译： 一种用于改善数据总线完整性的方法包括可以提高存储器系统中的数据总线的完整性的可选数据总线完整性特征。 外部控制器响应于要发送的相关数据产生纠错数据。 纠错数据被分成多个数据包并附加到相应的数据上，以便通过数据总线传输。 如果该功能被使能，存储器件可以使用ECC数据来尝试校正相应的数据并存储校正的数据和ECC数据。
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公开(公告)号：US20200004694A1
公开(公告)日：2020-01-02
申请号：US16023247
申请日：2018-06-29
摘要： Various examples are directed to systems and methods for managing a memory system. The memory system may generate a first encrypted physical address using a first clear physical address. The memory system may generate a first encrypted logical-to-physical (L2P) pointer indicating the first logical address and a first encrypted physical address. The memory system may send the first encrypted L2P pointer to a host device for storage at a host memory.
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公开(公告)号：US20130332783A1
公开(公告)日：2013-12-12
申请号：US13490633
申请日：2012-06-07
申请人： Alberto Troia
发明人： Alberto Troia
CPC分类号： G06F3/0619 , G06F3/0665 , G06F3/0689 , G06F11/10 , G06F11/1016 , G06F13/16
摘要： A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus.
摘要翻译： 一种用于提高存储器系统中的地址完整性的方法产生对应于存储器地址的纠错数据。 通过与通过命令总线发送无操作指令一致的地址总线将错误校正数据发送到存储器件。
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公开(公告)号：US09323608B2
公开(公告)日：2016-04-26
申请号：US13490690
申请日：2012-06-07
申请人： Alberto Troia
发明人： Alberto Troia
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0688 , G06F11/1048 , G11C16/26 , G11C29/52 , H03M13/13
摘要： A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An external controller generates error correction data in response to associated data to be transmitted. The error correction data is divided into multiple data packets and appended to the corresponding data for transmission over the data bus. The memory device can use the ECC data, if the feature is enabled, to attempt to correct the corresponding data and store both the corrected data and the ECC data.
摘要翻译： 一种用于改善数据总线完整性的方法包括可以提高存储器系统中的数据总线的完整性的可选数据总线完整性特征。 外部控制器响应于要发送的相关数据产生纠错数据。 纠错数据被分成多个数据包并附加到相应的数据上，以便通过数据总线传输。 如果该功能被使能，存储器件可以使用ECC数据来尝试校正相应的数据并存储校正的数据和ECC数据。
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公开(公告)号：US09009570B2
公开(公告)日：2015-04-14
申请号：US13490633
申请日：2012-06-07
申请人： Alberto Troia
发明人： Alberto Troia
CPC分类号： G06F3/0619 , G06F3/0665 , G06F3/0689 , G06F11/10 , G06F11/1016 , G06F13/16
摘要： A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus.
摘要翻译： 一种用于提高存储器系统中的地址完整性的方法产生对应于存储器地址的纠错数据。 通过与通过命令总线发送无操作指令一致的地址总线将错误校正数据发送到存储器件。
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公开(公告)号：US20200004679A1
公开(公告)日：2020-01-02
申请号：US16023485
申请日：2018-06-29
IPC分类号： G06F12/0802 , G06F12/1009 , G06F12/02 , H04L9/08 , H04L9/32
摘要： Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.
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