公开(公告)号：US07259580B2

公开(公告)日：2007-08-21

申请号：US10906483

申请日：2005-02-22

申请人： Paul J. Aube ,  Normand Cote ,  Roger G. Gamache, Jr. ,  David L. Gardell ,  Paul M. Gaschke ,  Marc D. Knox ,  Denis Turcotte

发明人： Paul J. Aube ,  Normand Cote ,  Roger G. Gamache, Jr. ,  David L. Gardell ,  Paul M. Gaschke ,  Marc D. Knox ,  Denis Turcotte

IPC分类号： G01R31/26

CPC分类号： G01R31/2875 ,  G01R31/2867 ,  G01R31/2868

摘要： A method, system and apparatus for testing an electronic device. The method including: (a) forming a temporary liquid heat transfer layer on a surface of the electronic device; after step (a), (b) placing a surface of a heat sink into physical contact with a surface of the heat transfer layer; after step (b), (c) electrically testing the electronic device; after step (c), (d) removing the heat sink from contact with the heat transfer layer; and after step (d), (e) removing any heat transfer layer remaining on the electronic device from the surface of the electronic device.

摘要翻译： 一种用于测试电子设备的方法，系统和装置。 该方法包括：（a）在电子设备的表面上形成临时液体传热层; 在步骤（a）之后，（b）将散热片的表面与传热层的表面物理接触; 在步骤（b）之后，（c）电测试电子设备; 在步骤（c）之后，（d）去除散热片与传热层的接触; 并且在步骤（d）之后，（e）从电子设备的表面去除残留在电子设备上的任何传热层。

公开(公告)号：US07332927B2

公开(公告)日：2008-02-19

申请号：US11743899

申请日：2007-05-03

申请人： Paul J. Aube ,  Normand Cote ,  Roger G. Gamache, Jr. ,  David L. Gardell ,  Paul M. Gaschke ,  Marc D. Knox ,  Denis D. Turcotte

发明人： Paul J. Aube ,  Normand Cote ,  Roger G. Gamache, Jr. ,  David L. Gardell ,  Paul M. Gaschke ,  Marc D. Knox ,  Denis D. Turcotte

IPC分类号： G01R31/26

CPC分类号： G01R31/2875 ,  G01R31/2867 ,  G01R31/2868

摘要： A method, system and apparatus for testing an integrated circuit chip. The system including: means for forming a liquid polyalphaolefine layer on a bottom surface of the integrated circuit chip, a top surface of the integrated circuit chip having and a bottom surface not having signal and power pads; means for placing a surface of a heat sink into physical contact with the bottom surface of the polyalphaolefine layer; means for electrically coupling the integrated circuit chip to a tester; means for electrically testing the integrated circuit chip; means for electrically de-coupling the integrated circuit chip from the tester; means for removing the heat sink from contact with the polyalphaolefine layer, all or a portion of the polyalphaolefine layer remaining on the bottom surface of the integrated circuit chip; and means for removing the polyalphaolefine layer from the bottom surface of the integrated circuit chip.

摘要翻译： 一种用于测试集成电路芯片的方法，系统和装置。 该系统包括：用于在集成电路芯片的底表面上形成液体聚α-烯烃层的装置，集成电路芯片的顶表面和没有信号和功率垫的底表面; 用于将散热器的表面放置成与聚α-烯烃精细层的底表面物理接触的装置; 用于将集成电路芯片电耦合到测试器的装置; 用于电测试集成电路芯片的装置; 用于将集成电路芯片与测试器电耦合的装置; 用于去除所述散热器与所述聚α-烯烃精氢层接触的装置，所述或部分所述聚α-烯烃精矿层残留在所述集成电路芯片的底表面上; 以及用于从集成电路芯片的底表面去除聚α-烯烃精细层的装置。

公开(公告)号：US6086387A

公开(公告)日：2000-07-11

申请号：US78769

申请日：1998-05-14

申请人： Ethan E. Gallagher ,  David L. Gardell ,  Paul M. Gaschke

发明人： Ethan E. Gallagher ,  David L. Gardell ,  Paul M. Gaschke

IPC分类号： G01R1/04 ,  G01R31/28 ,  H05K7/10 ,  H01R9/09

CPC分类号： H05K7/1061 ,  G01R1/0483 ,  G01R31/2863

摘要： A cover assembly for a socket suitable to accommodate modules of varying thicknesses which can be advantageously used for final test and burn-in test is described. The assembly is characterized by having a low profile and includes a hinged lid; a floating shaft coupled to two cams pivoting on the floating shaft; a locking member positioned between the two cams for locking the hinged lid when in a closed position, the locking member pivoting about the floating shaft; a pressure plate for forcing the module into the socket; and stiffening members integral to the hinged lid located on opposing sides of the hinged lid and below the surface of the pressure plate for providing added strength to the assembly. The assembly also includes a heatsink inserted through an aperture located in the pressure plate, to directly contact the chip which is mounted on the module. The force applied to the chip is independent of the force applied to the module.

摘要翻译： 描述了一种用于插座的盖组件，其适于容纳可用于最终测试和老化测试的不同厚度的模块。 组件的特征在于具有低轮廓并且包括铰接盖; 联接到在浮动轴上枢转的两个凸轮的浮动轴; 定位在所述两个凸轮之间的锁定构件，用于在处于关闭位置时锁定所述铰接盖，所述锁定构件围绕所述浮动轴枢转; 用于迫使模块进入插座的压板; 以及加强构件，其与位于铰接盖的相对侧上的铰接盖成一体，并且在压板的表面下方，用于为组件增加强度。 组件还包括通过位于压力板中的孔插入的散热器，以直接接触安装在模块上的芯片。 施加到芯片的力与施加到模块的力无关。

公开(公告)号：US06275051B1

公开(公告)日：2001-08-14

申请号：US09240121

申请日：1999-01-29

申请人： Thomas W. Bachelder ,  Dennis R. Barringer ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Paul M. Gaschke ,  Mark R. Laforce ,  Charles H. Perry ,  Roger R. Schmidt ,  Joseph J. Van Horn ,  Wade H. White

发明人： Thomas W. Bachelder ,  Dennis R. Barringer ,  Dennis R. Conti ,  James M. Crafts ,  David L. Gardell ,  Paul M. Gaschke ,  Mark R. Laforce ,  Charles H. Perry ,  Roger R. Schmidt ,  Joseph J. Van Horn ,  Wade H. White

IPC分类号： G01R1073

CPC分类号： G01R31/2863

摘要： An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.

摘要翻译： 用于在产品晶片上同时测试或燃烧大量集成电路芯片的装置包括安装在第一板上的探针和安装在第二板上的测试器芯片，连接两个板的电连接器。 测试器芯片用于向产品芯片分配电力或用于测试产品芯片。 其所附接的探针和薄膜布线被个性化以用于被探测的特定晶片的焊盘覆盖区。 第一板和第二板的基座对于产品系列中的所有晶片都保持不变。 使用两个电路板提供了测试器芯片在燃烧期间保持在比产品芯片基本上更低的温度，以延长测试器芯片的寿命。 间隙可以用作板之间的绝热，并将间隙密封并抽真空以进行进一步的隔热。 疏散还提供大气压力增加的接触，用于连接板和与晶片的接触。 用于平行测试芯片的探针被布置成月牙形条纹，以便与布置在区域阵列中的探针相比显着增加测试仪的吞吐量。

公开(公告)号：US06967556B2

公开(公告)日：2005-11-22

申请号：US10604185

申请日：2003-06-30

申请人： Paul M. Gaschke ,  Franco Motika

发明人： Paul M. Gaschke ,  Franco Motika

IPC分类号： G01R1/073 ,  H01F5/00

CPC分类号： G01R1/07378

摘要： A space transformer for use in an integrated circuit wafer test system, the space transformer including: a ground conductor; a power conductor; and one or more decoupling capacitors physically located between the ground conductor and the power conductor and electrically connected between a bottom surface of the ground conductor and a top surface of the power conductor.

摘要翻译： 一种用于集成电路晶片测试系统的空间变压器，所述空间变压器包括：接地导体; 电导体 以及物理上位于接地导体和电源导体之间并电连接在接地导体的底表面和电源导体的顶表面之间的一个或多个去耦电容器。

公开(公告)号：US06411112B1

公开(公告)日：2002-06-25

申请号：US09026382

申请日：1998-02-19

申请人： Gobinda Das ,  Steven J. Duda ,  Paul M. Gaschke

发明人： Gobinda Das ,  Steven J. Duda ,  Paul M. Gaschke

IPC分类号： G01R3102

CPC分类号： G01R1/07357 ,  G01R1/07371

摘要： A probe system for electrical contact testing of a row of densely spaced wire bonding pads is provided comprising a plurality of probes, with each probe having a tip offset from the probe center axis. The probes may be mounted in a housing having an upper die and a lower die, and the lower die may be offset from the upper die. The probes are pivotally mounted in the holes of the upper die, and the probe bodies are convexly curved and extend down into the holes of the lower die. The bevel tipped probes may be arranged in two staggered and parallel rows of probes, with the tip of each probe oriented along the centerline formed between the two row of probes. The probes may be closely spaced in each row. The tips of the probes in one row are oriented 180 degrees with respect to the probes in the opposite row. The tips of each probe may also comprise a tip located along the center axis or a double bevel surface forming a tip at the apex of the two bevel surfaces.

摘要翻译： 提供了一排密集间隔的引线接合焊盘的用于电接触测试的探针系统，其包括多个探针，每个探针具有从探针中心轴线偏移的尖端。 探针可以安装在具有上模和下模的壳体中，并且下模可以从上模偏移。 探针可枢转地安装在上模的孔中，并且探针体凸出地弯曲并向下延伸到下模的孔中。 倾斜尖端探针可以布置在两个交错和平行的探针中，每个探针的尖端沿着形成在两排探针之间的中心线取向。 探针可以在每排中紧密间隔开。 探针在一排中的尖端相对于相反行中的探针定向180度。 每个探针的尖端还可以包括沿着中心轴线定位的尖端或在两个斜面的顶点处形成尖端的双斜面。

公开(公告)号：US5088006A

公开(公告)日：1992-02-11

申请号：US691628

申请日：1991-04-25

申请人： Santiago E. del Puerto ,  Paul M. Gaschke

发明人： Santiago E. del Puerto ,  Paul M. Gaschke

IPC分类号： H01L21/66 ,  B23Q1/00 ,  H01L21/683

CPC分类号： H01L21/6838

摘要： A semiconductor wafer, liquid interface clamping and cooling system 80 includes a chuck 10 having clamping section 12 with a top surface 16 with three clamping/cooling circuit grooves machined therein for providing a liquid interface between a wafer under test and the top surface 16. A bottom surface 64 of the clamping section has a double spiral cooling circuit machined therein for providing backside cooling. A source vessel 110 maintained at atmospheric pressure provides fluid to the top surface clamping/cooling circuits and a collection vessel 112 maintained at house vacuum pressure collects the fluid. A set of processor controlled valves 114, 118, 128, 130, 132, 141, 142 144, 158 and 164 control the fluid in a preprogrammed sequence. A chiller system 82 and pump 90 provide temperature regulated fluid flow to the clamping section 12 bottom surface 64.

公开(公告)号：US20080143357A1

公开(公告)日：2008-06-19

申请号：US11610139

申请日：2006-12-13

申请人： Paul M. Gaschke ,  Karlheinz G. Schoenfeld

发明人： Paul M. Gaschke ,  Karlheinz G. Schoenfeld

IPC分类号： G01R1/067 ,  G01R31/26

CPC分类号： G01R1/0491

摘要： A high power Cobra interposer with an integrated guard plate, which is utilized for the testing of electrical products. The guard plate and the upper die of the interposer assembly are integrated into a single unit, thereby eliminating a portion of the structure. The Cobra structure utilizes a novel hole configuration in the upper die portion of the interposer structure, whereby only a small portion of the Cobra tip protrudes, rendering it less susceptible to being damaged in comparison with current designs.

摘要翻译： 具有综合防护板的高功率Cobra插入器，用于电气产品的测试。 防护板和插入器组件的上模被集成为单个单元，从而消除了结构的一部分。 眼镜蛇结构在内插器结构的上模部分中使用新颖的孔构造，由此仅眼镜蛇尖的一小部分突出，使得它与当前设计相比较不易受损。

公开(公告)号：US5001423A

公开(公告)日：1991-03-19

申请号：US469110

申请日：1990-01-24

申请人： Anthony J. Abrami ,  Stuart H. Bullard ,  Santiago E. del Puerto ,  Paul M. Gaschke ,  Mark R. LaForce ,  Paul J. Roggemann ,  Kort F. Longenbach

发明人： Anthony J. Abrami ,  Stuart H. Bullard ,  Santiago E. del Puerto ,  Paul M. Gaschke ,  Mark R. LaForce ,  Paul J. Roggemann ,  Kort F. Longenbach

IPC分类号： G01R31/28 ,  G05D23/19 ,  G05D23/20 ,  G05D23/24 ,  H01L21/66

CPC分类号： G01R31/2891 ,  G01R31/2831 ,  G03F7/707 ,  G03F7/70875

摘要： A wafer chuck temperature control system is disclosed for use in a semiconductor wafer testing apparatus. The wafer chuck is divided into a plurality of temperature sensor and cooling element domains corresponding to chip location regions of an overlying undiced wafer being tested. Computer scanning of the sensors determines which domain is the one harboring the heat source (chip under test) and selects the same for connection to a closed loop temperature control feedback servo. Provision also is made for introducing a helium gas interface between the wafer and the chuck by placing annular grooves in the face of the chuck through which the helium flows when the wafer is vacuum-seated against the chuck. A predetermined helium gas flow rate is maintained to preserve vacuum holddown and to optimize the thermal resistance of the wafer-chuck interface.

公开(公告)号：US06426636B1

公开(公告)日：2002-07-30

申请号：US09022240

申请日：1998-02-11

申请人： Gobinda Das ,  Steven J. Duda ,  Paul M. Gaschke ,  Angelo M. Giaimo ,  Frederick L. Taber, Jr. ,  John F. Vetrero

发明人： Gobinda Das ,  Steven J. Duda ,  Paul M. Gaschke ,  Angelo M. Giaimo ,  Frederick L. Taber, Jr. ,  John F. Vetrero

IPC分类号： G01R3102

CPC分类号： G01R1/0735

摘要： A nonresilient rigid test probe arrangement which is designed for testing the integrity of silicon semiconductor device wafers or chips, and which eliminates pliant conditions encountered by current text fixtures, which are adverse to the attainment of satisfactory test results with rigid probes. The test system interface assembly includes a rigid ceramic substrate which forms a pedestal over which the rigid probe makes electrical contact. A PC board is located on the opposite side of the ceramic substrate. A clamp ring retains the PC board to a test head system with mating precision reference surfaces formed therebetween. Pogo pin connectors extend between the PC board and the test head system. A stiffening element having a control aperture is bolted through the PC board to the clamp ring, all of which form a rigid test probe arrangement.

摘要翻译： 设计用于测试硅半导体器件晶片或芯片的完整性的非敏感性刚性测试探针装置，并且消除了当前文本夹具遇到的柔性条件，这对于用刚性探头达到令人满意的测试结果是不利的。 测试系统接口组件包括形成基座的刚性陶瓷基板，刚性探头在该基座上进行电接触。 PC板位于陶瓷基板的相对侧。 夹环将PC板保持在测试头系统上，其间形成有配合的精密参考表面。 Pogo针连接器在PC板和测试头系统之间延伸。 具有控制孔的加强元件通过PC板螺栓连接到夹紧环，所有这些形成刚性测试探针装置。