公开(公告)号：US4060794A

公开(公告)日：1977-11-29

申请号：US672103

申请日：1976-03-31

申请人： Paul S. Feldman ,  Robert B. Johnson ,  Chester M. Nibby, Jr.

发明人： Paul S. Feldman ,  Robert B. Johnson ,  Chester M. Nibby, Jr.

IPC分类号： G11C7/00 ,  G06F13/42 ,  G11C11/4076 ,  G11C11/408 ,  G06F13/00

CPC分类号： G06F13/4243 ,  G11C11/4076 ,  G11C11/408

摘要： Apparatus and a method for generating timing signals to be utilized in latched type memories only when the address signals are valid. A CAS signal is generated in response to an RAS signal via a device which tracks the worst case delay of memory address signals and does not permit the application of the CAS signal to memory until the worst case delay of the memory address signals has been accounted for.A memory array is comprised of any combination of latched or non-latched tri-state memories. The latched memories are coupled to a data bus utilizing conventional TTL circuits in combination with a power driver to simulate conventional tri-state buffer circuits. When the power driver/drivers remove(s) power from TTL circuits, the tri-state characteristics are simulated; whereas when the power driver applies power to the TTL circuits, they operate in their normal mode and present a normal impedance between the data bus and data-out lines of the memory array.

摘要翻译： 仅在地址信号有效时才产生用于锁存型存储器中的定时信号的装置和方法。 通过经追踪存储器地址信号的最坏情况延迟的设备产生响应于RAS信号的CAS信号，并且不允许将CAS信号应用于存储器，直到存储器地址信号的最差情况延迟已被考虑 。

公开(公告)号：US4451880A

公开(公告)日：1984-05-29

申请号：US202821

申请日：1980-10-31

申请人： Robert B. Johnson ,  Chester M. Nibby, Jr.

发明人： Robert B. Johnson ,  Chester M. Nibby, Jr.

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F13/28 ,  H04L25/49 ,  G06F13/00

CPC分类号： G06F13/1642 ,  G06F13/28

摘要： A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.

摘要翻译： 存储器控制器控制多个存储器模块单元的操作，并且包括耦合到模块单元的多个队列。 每个队列包括地址队列寄存器，控制队列寄存器和数据队列寄存器。 每个地址队列寄存器都有三态控制，用于独立操作。 当队列控制寄存器存储正在处理的请求时，耦合到队列地址，控制和数据寄存器的控制电路在备用的队列之间分配存储器周期。 这使得能够消除处理延迟的存储器请求的交织，特别是在这种请求涉及在连续存储器操作周期中的多字传输的情况下。

公开(公告)号：US4376972A

公开(公告)日：1983-03-15

申请号：US110521

申请日：1980-01-08

申请人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Dana W. Moore

发明人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Dana W. Moore

IPC分类号： G11C11/401 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F13/12 ,  G06F13/00

CPC分类号： G06F12/04 ,  G06F12/02

摘要： A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.

摘要翻译： 耦合到多字总线以用于处理从其接收的存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。 每个存储器单元包括多行随机存取存储器（RAM）芯片。 子系统还包括加法器电路，一对三态操作地址寄存器电路和定时电路。 地址电路包括一对三态操作地址寄存器，其耦合到总线和到每个存储器单元的地址线集合。 响应于存储器请求，寄存器存储存储器请求的芯片地址的行和列地址部分。 当存储器请求的最低有效地址位指示子边界地址条件从而使得能够访问一对顺序字位置时，多位加法器电路被连接以递增一个低位行地址。 每当存储器请求指定不能访问双字的地址时，边界电路在检测到条件时，使定时电路仅产生访问第一字位置所必需的定时信号。

公开(公告)号：US4545010A

公开(公告)日：1985-10-01

申请号：US480964

申请日：1983-03-31

申请人： Edward R. Salas ,  Edwin P. Fisher ,  Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Daniel A. Boudreau

发明人： Edward R. Salas ,  Edwin P. Fisher ,  Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Daniel A. Boudreau

IPC分类号： G06F12/06 ,  G06F13/00

CPC分类号： G06F12/0653

摘要： A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.

摘要翻译： 存储器系统包括至少一个或多个存储器模块板，其结构相同，以及包含用于控制存储器操作的控制电路的单个计算机板。 每个板插入主板，并且包括具有多行存储器芯片的存储器部分和用于产生指示板密度的信号的电路的识别部分和用于构建电路板存储部分的存储器部件的类型的识别部分。 主板控制电路包括耦合到每个存储器模块板的识别和存储器部分的多个解码器电路。 解码器电路接收每个存储器请求地址的预定多位地址部分的不同地址位组合。 响应于由所安装的存储器板的识别部分产生的信号，解码器电路被选择性地能够解码由这些部分指定的地址部分的那些比特组合，以便能够对系统内的所有位置块进行连续寻址。

公开(公告)号：US4359771A

公开(公告)日：1982-11-16

申请号：US172486

申请日：1980-07-25

申请人： Robert B. Johnson ,  Chester M. Nibby, Jr.

发明人： Robert B. Johnson ,  Chester M. Nibby, Jr.

IPC分类号： G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/267 ,  G11C11/406 ,  G11C29/00 ,  G11C29/42

CPC分类号： G06F11/2215 ,  G06F11/106 ,  G11C11/406

摘要： Soft error rewrite control apparatus is included within a memory system for rendering the semiconductor memory modules less susceptible to single bit errors produced by alpha particles and other system disturbances. During a number of successive memory cycles occurring at a predetermined rate, the soft error rewrite control apparatus enables the read out of information stored within each module location, the correction of any single bit errors contained therein and the rewriting of the corrected information back into such location. Diagnostic apparatus is further included which is connected to place the memory system in a state for testing and verifying the operation of the soft error control apparatus. Also, the diagnostic apparatus is connected to condition the soft error control apparatus for operating in a high speed mode enabling the read out correction and rewriting of each location to take place within a minimum amount of time. By monitoring the status of the information being corrected, the diagnostic apparatus is able to signal whether or not the soft error control apparatus is operating properly.

摘要翻译： 软错误重写控制装置包括在存储器系统内，用于使半导体存储器模块不易受由α粒子和其他系统干扰产生的单位错误的影响。 在以预定速率发生的多个连续存储循环期间，软错误重写控制装置使得能够读出存储在每个模块位置内的信息，校正其中包含的任何单个位错误，以及将校正后的信息重新写入其中 位置。 还包括诊断装置，其连接以将存储器系统置于用于测试和验证软错误控制装置的操作的状态。 此外，诊断装置被连接以对软错误控制装置进行调整，以便在高速模式下操作，使得能够在最小时间内进行每个位置的读出校正和重写。 通过监视正在修正的信息的状态，诊断装置能够通知软错误控制装置是否正常工作。

公开(公告)号：US4255852A

公开(公告)日：1981-03-17

申请号：US57783

申请日：1979-07-16

申请人： Robert B. Johnson ,  Chester M. Nibby, Jr.

发明人： Robert B. Johnson ,  Chester M. Nibby, Jr.

IPC分类号： H05K1/00 ,  H05K1/11 ,  H05K3/32

CPC分类号： H05K1/116 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/0298 ,  H05K2201/09954 ,  H05K2201/10689 ,  Y10T29/49139

摘要： A printed circuit board assembly includes at least two layers which is able to accommodate a subsystem such as a memory subsystem designed to have one or more optional features. The two layers of the printed circuit board when etched include the required number of horizontal and vertical paths to be connected to all of the integrated circuit chips to be positioned and interconnected thereon. The required holes for such integrated circuit chips when drilled include first sets of holes for mounting groups of integrated circuit chips required for implementing a first group of features and which are to be interconnected to the other integrated circuit chips of the subsystem mounted on the different sections of the board. Second sets of holes are included on the board so as to have a predetermined relationship with the first sets of holes for mounting alternative groups of integrated circuit chips to be interconnected in a manner to implement other features. Thereafter, the circuit board is populated with only those integrated circuit chips required for construction of a memory subsystem with one or more selected features.

摘要翻译： 印刷电路板组件包括至少两层，其能够容纳诸如设计成具有一个或多个可选特征的存储器子系统的子系统。 当蚀刻时，印刷电路板的两层包括要连接到要定位和互连在其上的所有集成电路芯片的所需数量的水平和垂直路径。 用于这种集成电路芯片的所需的孔在钻孔时包括用于实现第一组特征所需的集成电路芯片组的第一组孔，并且其将被连接到安装在不同部分上的子系统的其它集成电路芯片 的董事会。 第二组孔包括在板上，以便与第一组孔相关联，以便以相互连接的替代的集成电路芯片组来实现其他特征。 此后，电路板仅填充用于构造具有一个或多个所选特征的存储器子系统所需的那些集成电路芯片。

公开(公告)号：US4468731A

公开(公告)日：1984-08-28

申请号：US330971

申请日：1981-12-15

申请人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Edward R. Salas

发明人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Edward R. Salas

IPC分类号： G06F11/22 ,  G06F11/10

CPC分类号： G06F11/22

摘要： A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

摘要翻译： 一种数据处理系统包括一个与中央处理单元共同耦合到总线的主存储系统，用于在中央处理单元和存储器系统之间传送数据。 存储器系统包括多个存储器控制器，每个存储器控制器控制多个存储器模块的操作。 每个控制器还包括重新配置装置，用于在检测到故障时能够重新配置存储器系统。 重新配置装置包括用于识别与其相关联的控制器的类型和设计版本的装置，其基于由中央处理单元在诊断测试期间由控制器提供的状态信号进行更快速的故障诊断。

公开(公告)号：US4366539A

公开(公告)日：1982-12-28

申请号：US202819

申请日：1980-10-31

申请人： Robert B. Johnson ,  Chester M. Nibby, Jr.

发明人： Robert B. Johnson ,  Chester M. Nibby, Jr.

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/16

摘要： A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.

摘要翻译： 存储器控制器，其耦合到多个存储器模块单元并且包括多个控制电路。 控制电路包括地址计数器电路，其中装载有来自请求装置的每个预定类型的命令或存储器请求的地址的一部分。 当解码时，该命令使得控制器从存储器模块单元读出由存储的地址部分指定的位置开始的预定数量的字对。

公开(公告)号：US4323965A

公开(公告)日：1982-04-06

申请号：US110523

申请日：1980-01-08

申请人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Dana Moore

发明人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Dana Moore

IPC分类号： G11C11/406 ,  G06F12/04 ,  G06F12/06 ,  G06F13/00

CPC分类号： G06F12/04 ,  G06F12/0607

摘要： A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.

摘要翻译： 耦合到多字总线以用于处理从其接收的存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。 每个存储器单元包括多行随机存取存储器（RAM）芯片。 子系统作为每个存储器请求的一部分接收一个地址，其中最不重要的部分在一对存储器单元之一内选择要访问的芯片行。 地址解码电路包括耦合到两个模块单元的选通电路。 门控电路互连，使得对最低有效地址位的解码导致产生一对行地址选通信号。 这些信号同时支持RAM芯片的行，以在两个模块单元内进行访问，以将信息读出到多字总线，从而消除地址递增的任何延迟。

公开(公告)号：US4236203A

公开(公告)日：1980-11-25

申请号：US867270

申请日：1978-01-05

申请人： John L. Curley ,  Robert B. Johnson ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

发明人： John L. Curley ,  Robert B. Johnson ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/368 ,  G06F13/37 ,  G06F13/42 ,  G06F1/04

CPC分类号： G06F13/368 ,  G06F13/4213

摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.

摘要翻译： 在包括公共总线的系统中，诸如数据处理系统的用于传送信息的多个单元连接到该公共总线，在异步生成的总线传送周期期间，信息可以由最高优先级请求单元传送。 逻辑被提供用于实现多次提取操作，其中主单元在第一总线传送周期期间从从单元请求多个信息字可以在一系列随后从站产生的总线周期期间从从单元接收这些信息。 逻辑被提供用于使得任何其他单元能够在第一周期与从单元响应的最后周期之间的时间内通过公共总线进行通信，从而使得至少两对单元能够分别在交织的 方式。