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    Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the same
    5.
    发明申请
    Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the same 审中-公开
    具有非标准晶体取向的半导体晶片及其制造方法

    公开(公告)号：US20050217560A1

    公开(公告)日：2005-10-06

    申请号：US10815427

    申请日：2004-03-31

    申请人： Peter Tolchinsky ,  Mohamad Shaheen ,  Irwin Yablok

    发明人： Peter Tolchinsky ,  Mohamad Shaheen ,  Irwin Yablok

    IPC分类号： C30B1/00 ,  C30B15/36 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  H01L21/762

    CPC分类号： H01L21/76256 ,  C30B15/36 ,  H01L21/76254

    摘要： The crystal orientations of monocrystalline semiconductor wafers may be varied by four parameters. The first parameter is the type of crystal seed used to grow the monocrystalline semiconductor ingot from which the wafers are cut. The second parameter is the angle at which the wafer is sliced from the ingot. The third parameter is the crystal plane towards which the wafer is cut. And, the fourth parameter is the position of the orientation indication feature that is used to align the wafer during processing. Different combinations of these parameters provide variations of non-standard crystal orientations of monocrystalline semiconductor wafers and semiconductor-on-insulator substrates such as silicon-on-insulator.

    摘要翻译： 单晶半导体晶片的晶体取向可以通过四个参数来改变。 第一个参数是用于生长切割晶片的单晶半导体晶锭的晶种种类。 第二个参数是从晶锭切片晶片的角度。 第三参数是切割晶片的晶体平面。 而且，第四参数是在处理期间用于对准晶片的取向指示特征的位置。 这些参数的不同组合提供单晶半导体晶片和绝缘体上半导体衬底（例如绝缘体上硅）的非标准晶体取向的变化。

    Insulation layer for silicon-on-insulator wafer
    6.
    发明申请
    Insulation layer for silicon-on-insulator wafer 审中-公开
    绝缘体上硅晶片绝缘层

    公开(公告)号：US20070063279A1

    公开(公告)日：2007-03-22

    申请号：US11231002

    申请日：2005-09-16

    申请人： Peter Tolchinsky ,  Mohamad Shaheen ,  Martin Giles ,  Irwin Yablok ,  Aaron Budrevich

    发明人： Peter Tolchinsky ,  Mohamad Shaheen ,  Martin Giles ,  Irwin Yablok ,  Aaron Budrevich

    IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L21/84 ,  H01L21/00

    CPC分类号： H01L21/76243

    摘要： A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that remains substantially free of oxygen between the oxygen layer and the first surface. An annealing process is then used to diffuse nitrogen into the silicon wafer, wherein the nitrogen diffuses into the silicon device layer and the oxygen layer. Finally, a second annealing process is used to form a silicon dioxide layer and a silicon oxynitride layer, wherein the second annealing process causes the implanted oxygen to react with the silicon to form the silicon dioxide layer and causes the diffused nitrogen to migrate and react with the silicon and the implanted oxygen to form the silicon oxynitride layer.

    摘要翻译： 形成绝缘体上硅晶片的方法开始于提供具有第一表面的硅晶片。 然后使用离子注入工艺将氧气注入到硅晶片内以形成掩埋在硅晶片内的氧层，由此形成在氧层和第一表面之间基本上不含氧的硅器件层。 然后使用退火工艺将氮扩散到硅晶片中，其中氮扩散到硅器件层和氧层中。 最后，使用第二退火工艺形成二氧化硅层和氧氮化硅层，其中第二退火工艺使注入的氧与硅反应形成二氧化硅层，并使扩散的氮迁移并与 硅和注入的氧以形成氮氧化硅层。

    Methods of vertically stacking wafers using porous silicon
    7.
    发明申请
    Methods of vertically stacking wafers using porous silicon 有权
    使用多孔硅垂直堆叠晶圆的方法

    公开(公告)号：US20060138627A1

    公开(公告)日：2006-06-29

    申请号：US11025131

    申请日：2004-12-29

    申请人： Mohamad Shaheen ,  Peter Tolchinsky ,  Irwin Yablok ,  Scott List

    发明人： Mohamad Shaheen ,  Peter Tolchinsky ,  Irwin Yablok ,  Scott List

    IPC分类号： H01L21/30 ,  H01L23/02

    CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L21/76259 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2924/01033 ,  H01L2924/14

    摘要： A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

    摘要翻译： 一种提供三维（3-D）IC晶片工艺流程的方法和制品。 在一些实施例中，所述方法和制品包括将多层晶片的器件层接合到另一多层晶片的器件层以形成键合的器件层对，所述多层晶片中的每一个在多孔硅层上包括硅层 （SiOPSi），其中所述器件层形成在所述硅层中，通过分离所述多孔硅层之一将所述一对器件层与所述硅衬底中的一个分离，并且将所述一对器件层与所述多个硅层分离 通过分离另一个多孔硅层来提供剩余的硅衬底以提供垂直堆叠的晶片。