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公开(公告)号：US20130169457A1
公开(公告)日：2013-07-04
申请号：US13724182
申请日：2012-12-21
CPC分类号： H03M1/12 , G04F10/005 , G04F10/105 , H03M1/1009 , H03M1/1023 , H03M1/50
摘要： A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.
摘要翻译： 电阻/剩余电荷数字定时器（RCDT）通过将时间延迟转换为电流，并测量电容器在一段持续时间内积分的电荷，可以有效，准确地测量两个信号之间的短时间延迟。 在一个实施例中，在量化该电荷（以电压测量）时，剩余电荷被周期性地保持。 这允许对数字定时器（NCDT）实现噪声整形充电，在多个测量周期内提供改进的分辨率。 RCDT / NCDT特别（但不排他地）非常适合数字锁相环中的相位误差检测。
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公开(公告)号：US20130169327A1
公开(公告)日：2013-07-04
申请号：US13338390
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
发明人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
CPC分类号： H03L7/06 , G04F10/005 , G04F10/105
摘要： The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
摘要翻译： 这里公开的电荷数字计时装置和方法估计两个信号之间的经过时间，例如起始信号和停止信号。 为此，至少电容性负载以已知电流充电以产生负载电压。 随后，第一电压以与多个已知电容相关联的多个离散电压阶跃斜坡，直到斜坡电压相对于第二电压满足预定标准。 经过的时间由离散的电压阶跃确定，第一和第二电压之一，已知电流和已知的容性负载。
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公开(公告)号：US09379729B2
公开(公告)日：2016-06-28
申请号：US13724182
申请日：2012-12-21
CPC分类号： H03M1/12 , G04F10/005 , G04F10/105 , H03M1/1009 , H03M1/1023 , H03M1/50
摘要： A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.
摘要翻译： 电阻/剩余电荷数字定时器（RCDT）通过将时间延迟转换为电流，并测量电容器在一段持续时间内积分的电荷，可以有效，准确地测量两个信号之间的短时间延迟。 在一个实施例中，在量化该电荷（以电压测量）时，剩余电荷被周期性地保持。 这允许对数字定时器（NCDT）实现噪声整形充电，在多个测量周期内提供改进的分辨率。 RCDT / NCDT特别（但不排他地）非常适合数字锁相环中的相位误差检测。
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公开(公告)号：US08659360B2
公开(公告)日：2014-02-25
申请号：US13338390
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
发明人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
CPC分类号： H03L7/06 , G04F10/005 , G04F10/105
摘要： The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
摘要翻译： 这里公开的电荷数字计时装置和方法估计两个信号之间的经过时间，例如起始信号和停止信号。 为此，至少电容性负载以已知电流充电以产生负载电压。 随后，第一电压以与多个已知电容相关联的多个离散电压阶跃斜坡，直到斜坡电压相对于第二电压满足预定标准。 经过的时间由离散的电压阶跃确定，第一和第二电压之一，已知电流和已知的容性负载。
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公开(公告)号：US08618965B2
公开(公告)日：2013-12-31
申请号：US13338550
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Paavo Väänänen
发明人： Petri Heliö , Petri Korpi , Paavo Väänänen
IPC分类号： H03M1/10
CPC分类号： G04F10/105
摘要： A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.
摘要翻译： 本文公开的校准方法校准控制电荷数字定时器（CDT）的容性负载和充电电流中的至少一个。 通常，所公开的校准方法基于由已知时间差分开的起始和停止信号来测量多个校准相位，并且因此具有已知的相位，并且基于所述的相位调整CDT的容性负载和充电电流中的至少一个 测量校准阶段。 这样做，所公开的校准方法降低了在CDT的频率范围上的功率耗散和峰值电源电流。
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公开(公告)号：US20130169455A1
公开(公告)日：2013-07-04
申请号：US13338550
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Paavo Väänänen
发明人： Petri Heliö , Petri Korpi , Paavo Väänänen
IPC分类号： H03M1/10
CPC分类号： G04F10/105
摘要： A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.
摘要翻译： 本文公开的校准方法校准控制电荷数字定时器（CDT）的容性负载和充电电流中的至少一个。 通常，所公开的校准方法基于由已知时间差分开的起始和停止信号来测量多个校准相位，并且因此具有已知的相位，并且基于所述的相位调整CDT的容性负载和充电电流中的至少一个 测量校准阶段。 这样做，所公开的校准方法降低了在CDT的频率范围上的功率耗散和峰值电源电流。
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公开(公告)号：US20140211895A1
公开(公告)日：2014-07-31
申请号：US14236431
申请日：2012-08-02
申请人： Niko Mikkola , Petri Heliö , Paavo Väänänen
发明人： Niko Mikkola , Petri Heliö , Paavo Väänänen
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H03K23/667 , H03K23/68
摘要： A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
摘要翻译： 分频器包括信号产生级，被配置为以时钟频率采用时钟来提供第一参考信号和第二参考信号，第二参考信号对应于延迟了时钟信号的一半周期的第一参考信号。 同步级被布置成通过在输出信号的每个周期一次切换第一参考信号和第二参考信号来产生具有从时钟频率划分的输出频率的输出信号。
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公开(公告)号：US07764938B2
公开(公告)日：2010-07-27
申请号：US11707865
申请日：2007-02-20
申请人： Petri Heliö , Paavo Väänänen , Niko Mikkola , Jouni Kinnunen
发明人： Petri Heliö , Paavo Väänänen , Niko Mikkola , Jouni Kinnunen
IPC分类号： H04B1/06
摘要： The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.
摘要翻译： 所提出的装置并且用于通过复用信号产生信号，使得在输出信号中没有毛刺。 本装置利用被复用的输入振荡器信号之间的相位差的知识，以提供无毛刺输出信号。 该装置包括第一选择电路，其被配置为将其响应与第一控制信号同步到输入振荡器信号之一的下一个确定的事件，并且响应于第一控制信号将输入振荡器信号传送到其输出。 该装置包括被复用的每个输入振荡器信号的类似选择电路。 选择电路的输出可以连接到组合输出的组合电路，从而提供无毛刺的输出信号。
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公开(公告)号：US07142062B2
公开(公告)日：2006-11-28
申请号：US11027563
申请日：2004-12-30
申请人： Paavo Väänänen , Petri Heliö
发明人： Paavo Väänänen , Petri Heliö
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03J7/023 , H03J7/10 , H03J2200/10 , H03J2200/29 , H03J2200/36 , H03L7/099
摘要： This invention describes a method for simultaneous precise center frequency tuning and limiting a gain variation of a voltage controlled oscillator (VCO) of a phase locked loop (PLL) of an electronic device (e.g., a communication device, a mobile electronic device, a mobile phone, etc.). The invention utilizes frequency measurements and arithmetical optimizations. More specifically, the invention implementation is based on an analysis which includes measuring a frequency of a VCO and calculating a gain of the voltage controlled oscillator (VCO) using a predetermined criterion. The key element for implementing said analysis is a control and arithmetic block. The present invention can be used in any radio architecture that requires limiting of the VCO gain variation and tuning its center frequency.
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公开(公告)号：US09485079B2
公开(公告)日：2016-11-01
申请号：US14236431
申请日：2012-08-02
申请人： Niko Mikkola , Petri Heliö , Paavo Väänänen
发明人： Niko Mikkola , Petri Heliö , Paavo Väänänen
CPC分类号： H04L7/0008 , H03K23/667 , H03K23/68
摘要： A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronization stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.
摘要翻译： 分频器包括信号产生级，被配置为以时钟频率采用时钟来提供第一参考信号和第二参考信号，第二参考信号对应于延迟了时钟信号的一半周期的第一参考信号。 同步级被布置成通过在输出信号的每个周期一次切换第一参考信号和第二参考信号来产生具有从时钟频率划分的输出频率的输出信号。
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