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公开(公告)号：US20130169327A1
公开(公告)日：2013-07-04
申请号：US13338390
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
发明人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
CPC分类号： H03L7/06 , G04F10/005 , G04F10/105
摘要： The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
摘要翻译： 这里公开的电荷数字计时装置和方法估计两个信号之间的经过时间，例如起始信号和停止信号。 为此，至少电容性负载以已知电流充电以产生负载电压。 随后，第一电压以与多个已知电容相关联的多个离散电压阶跃斜坡，直到斜坡电压相对于第二电压满足预定标准。 经过的时间由离散的电压阶跃确定，第一和第二电压之一，已知电流和已知的容性负载。
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公开(公告)号：US08659360B2
公开(公告)日：2014-02-25
申请号：US13338390
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
发明人： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
CPC分类号： H03L7/06 , G04F10/005 , G04F10/105
摘要： The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
摘要翻译： 这里公开的电荷数字计时装置和方法估计两个信号之间的经过时间，例如起始信号和停止信号。 为此，至少电容性负载以已知电流充电以产生负载电压。 随后，第一电压以与多个已知电容相关联的多个离散电压阶跃斜坡，直到斜坡电压相对于第二电压满足预定标准。 经过的时间由离散的电压阶跃确定，第一和第二电压之一，已知电流和已知的容性负载。
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公开(公告)号：US20130169457A1
公开(公告)日：2013-07-04
申请号：US13724182
申请日：2012-12-21
CPC分类号： H03M1/12 , G04F10/005 , G04F10/105 , H03M1/1009 , H03M1/1023 , H03M1/50
摘要： A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.
摘要翻译： 电阻/剩余电荷数字定时器（RCDT）通过将时间延迟转换为电流，并测量电容器在一段持续时间内积分的电荷，可以有效，准确地测量两个信号之间的短时间延迟。 在一个实施例中，在量化该电荷（以电压测量）时，剩余电荷被周期性地保持。 这允许对数字定时器（NCDT）实现噪声整形充电，在多个测量周期内提供改进的分辨率。 RCDT / NCDT特别（但不排他地）非常适合数字锁相环中的相位误差检测。
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公开(公告)号：US09379729B2
公开(公告)日：2016-06-28
申请号：US13724182
申请日：2012-12-21
CPC分类号： H03M1/12 , G04F10/005 , G04F10/105 , H03M1/1009 , H03M1/1023 , H03M1/50
摘要： A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.
摘要翻译： 电阻/剩余电荷数字定时器（RCDT）通过将时间延迟转换为电流，并测量电容器在一段持续时间内积分的电荷，可以有效，准确地测量两个信号之间的短时间延迟。 在一个实施例中，在量化该电荷（以电压测量）时，剩余电荷被周期性地保持。 这允许对数字定时器（NCDT）实现噪声整形充电，在多个测量周期内提供改进的分辨率。 RCDT / NCDT特别（但不排他地）非常适合数字锁相环中的相位误差检测。
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公开(公告)号：US08618965B2
公开(公告)日：2013-12-31
申请号：US13338550
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Paavo Väänänen
发明人： Petri Heliö , Petri Korpi , Paavo Väänänen
IPC分类号： H03M1/10
CPC分类号： G04F10/105
摘要： A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.
摘要翻译： 本文公开的校准方法校准控制电荷数字定时器（CDT）的容性负载和充电电流中的至少一个。 通常，所公开的校准方法基于由已知时间差分开的起始和停止信号来测量多个校准相位，并且因此具有已知的相位，并且基于所述的相位调整CDT的容性负载和充电电流中的至少一个 测量校准阶段。 这样做，所公开的校准方法降低了在CDT的频率范围上的功率耗散和峰值电源电流。
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公开(公告)号：US20130169455A1
公开(公告)日：2013-07-04
申请号：US13338550
申请日：2011-12-28
申请人： Petri Heliö , Petri Korpi , Paavo Väänänen
发明人： Petri Heliö , Petri Korpi , Paavo Väänänen
IPC分类号： H03M1/10
CPC分类号： G04F10/105
摘要： A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.
摘要翻译： 本文公开的校准方法校准控制电荷数字定时器（CDT）的容性负载和充电电流中的至少一个。 通常，所公开的校准方法基于由已知时间差分开的起始和停止信号来测量多个校准相位，并且因此具有已知的相位，并且基于所述的相位调整CDT的容性负载和充电电流中的至少一个 测量校准阶段。 这样做，所公开的校准方法降低了在CDT的频率范围上的功率耗散和峰值电源电流。
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公开(公告)号：US20100283032A1
公开(公告)日：2010-11-11
申请号：US12598368
申请日：2008-03-31
申请人： Petri Korpi , Risto Ronkka
发明人： Petri Korpi , Risto Ronkka
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y20/00 , B82Y30/00 , H01L21/02381 , H01L21/02422 , H01L21/02425 , H01L21/02488 , H01L21/02532 , H01L21/02601 , H01L21/02628 , H01L27/1292 , H01L29/0665 , H01L51/0541 , H01L51/0562 , H01L51/0566 , H01L2251/5369
摘要： Method for Forming a Semiconductor Structure A method and apparatus for applying a carrier fluid (101,602,1101) to a substrate (102), the carrier fluid carrying nanoparticles (201,202), manipulating the positions of a plurality of the nanoparticles (201,202) in the carrier fluid by applying an electric field, removing the carrier fluid from the substrate so as to leave the nanoparticles on the substrate, and sintering the nanoparticles to form a region.
摘要翻译： 用于形成半导体结构的方法用于将载体流体（101,602,1101）施加到基底（102）上的载体流体携带纳米颗粒（201,202）的方法和装置，其操作多个纳米颗粒（201,202）中的位置 载体流体通过施加电场，从衬底去除载体流体以使纳米颗粒离开衬底，并烧结纳米颗粒以形成区域。
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