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公开(公告)号：US08530886B2
公开(公告)日：2013-09-10
申请号：US13051707
申请日：2011-03-18
IPC分类号： H01L29/12
CPC分类号： H01L29/518 , H01L29/1606 , H01L29/42384 , H01L29/4908 , H01L29/78684
摘要： A semiconductor structure which includes a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode; and a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.
摘要翻译： 一种包括衬底的半导体结构; 基板上的石墨烯层; 在石墨烯层上的源电极和漏电极，源电极和漏极间隔开预定尺寸; 在源电极和漏电极之间的石墨烯层上的氮化物层; 以及氮化物层上的栅极电极，其中氮化物层是用于栅电极的栅极电介质。
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公开(公告)号：US20120235118A1
公开(公告)日：2012-09-20
申请号：US13051707
申请日：2011-03-18
申请人： Phaedon Avouris , Deborah Neumayer , Wenjuan Zhu
发明人： Phaedon Avouris , Deborah Neumayer , Wenjuan Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/518 , H01L29/1606 , H01L29/42384 , H01L29/4908 , H01L29/78684
摘要： A semiconductor structure which includes a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode; and a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.
摘要翻译： 一种包括衬底的半导体结构; 基板上的石墨烯层; 在石墨烯层上的源电极和漏电极，源电极和漏极间隔开预定尺寸; 在源电极和漏电极之间的石墨烯层上的氮化物层; 以及氮化物层上的栅极电极，其中氮化物层是用于栅电极的栅极电介质。
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3.发明授权Graphene devices and semiconductor field effect transistors in 3D hybrid integrated circuits 有权石墨烯装置和3D混合集成电路中的半导体场效应晶体管公开(公告)号：US08748871B2
公开(公告)日：2014-06-10
申请号：US13352737
申请日：2012-01-18
申请人： Phaedon Avouris , Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu , Yanqing Wu , Wenjuan Zhu
发明人： Phaedon Avouris , Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L27/088
CPC分类号： H01L27/0688 , B82Y10/00 , H01L29/1606 , H01L29/78684
摘要： A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.
摘要翻译： 三维集成电路包括半导体器件，形成在半导体器件上的绝缘体，形成在绝缘体中的互连以及形成在绝缘体上的石墨烯器件。
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4.发明申请Graphene Devices and Semiconductor Field Effect Transistors in 3D Hybrid Integrated Circuits 有权石墨烯器件和3D混合集成电路中的半导体场效应晶体管公开(公告)号：US20120181510A1
公开(公告)日：2012-07-19
申请号：US13352737
申请日：2012-01-18
申请人： Phaedon Avouris , Yanqing Wu , Wenjuan Zhu
发明人： Phaedon Avouris , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L27/088 , H01L21/336 , H01L21/28 , B82Y40/00 , B82Y99/00
CPC分类号： H01L27/0688 , B82Y10/00 , H01L29/1606 , H01L29/78684
摘要： A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.
摘要翻译： 三维集成电路包括半导体器件，形成在半导体器件上的绝缘体，形成在绝缘体中的互连以及形成在绝缘体上的石墨烯器件。
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5.发明申请BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES 失效用于石墨设备的低等效氧化物厚度的双层栅介质公开(公告)号：US20130207080A1
公开(公告)日：2013-08-15
申请号：US13369901
申请日：2012-02-09
申请人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
发明人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L21/0237 , B82Y30/00 , B82Y40/00 , H01L21/02378 , H01L21/02527 , H01L21/02617 , H01L21/02661 , H01L29/1606 , H01L29/4908 , H01L29/513 , H01L29/66045 , H01L29/7781 , H01L29/78684
摘要： A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
摘要翻译： 在石墨烯层的最上表面上设置氮化硅层，然后在氮化硅层的最上表面上设置二氧化铪层。 氮化硅层用作二氧化铪层的润湿剂，从而防止在石墨烯层顶上形成不连续的二氧化铪塔。 共同形成低EOT双层栅极电介质的氮化硅层和二氧化铪层在石墨烯层的顶部呈现连续的形态。
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6.发明授权Bilayer gate dielectric with low equivalent oxide thickness for graphene devices 失效双层栅极电介质，石墨烯器件的等效氧化物厚度低公开(公告)号：US08680511B2
公开(公告)日：2014-03-25
申请号：US13369901
申请日：2012-02-09
申请人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
发明人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
IPC分类号： H01L29/06
CPC分类号： H01L21/0237 , B82Y30/00 , B82Y40/00 , H01L21/02378 , H01L21/02527 , H01L21/02617 , H01L21/02661 , H01L29/1606 , H01L29/4908 , H01L29/513 , H01L29/66045 , H01L29/7781 , H01L29/78684
摘要： A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
摘要翻译： 在石墨烯层的最上表面上设置氮化硅层，然后在氮化硅层的最上表面上设置二氧化铪层。 氮化硅层用作二氧化铪层的润湿剂，从而防止在石墨烯层顶上形成不连续的二氧化铪塔。 共同形成低EOT双层栅极电介质的氮化硅层和二氧化铪层在石墨烯层的顶部呈现连续的形态。
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公开(公告)号：US08564027B2
公开(公告)日：2013-10-22
申请号：US13359647
申请日：2012-01-27
申请人： Wenjuan Zhu
发明人： Wenjuan Zhu
IPC分类号： H01L29/84
CPC分类号： H01L29/78606 , B81B2201/038 , B81B2203/0127 , B81C1/00158 , B82Y30/00 , H01L29/1606 , H01L29/4908 , H01L29/66045 , H01L29/78603 , H01L29/78648 , H01L29/78684
摘要： Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices.
摘要翻译： 使用悬浮在半导体结构的开放腔之间的石墨烯膜构造的半导体纳米器件，例如纳米探针和纳米刀装置。 悬浮的石墨烯膜用作可以从一个或几个原子厚度制成非常薄的电子机械膜，以大大提高半导体纳米探针和纳米刀装置的灵敏度和可靠性。
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8.发明申请GRAPHENE TRANSISTOR GATED BY CHARGES THROUGH A NANOPORE FOR BIO-MOLECULAR SENSING AND DNA SEQUENCING 有权用于生物分子传感和DNA测序的纳米级电荷的石墨晶体管公开(公告)号：US20130271150A1
公开(公告)日：2013-10-17
申请号：US13477099
申请日：2012-05-22
申请人： Hongbo Peng , Gustavo A. Stolovitzky , Wenjuan Zhu
发明人： Hongbo Peng , Gustavo A. Stolovitzky , Wenjuan Zhu
CPC分类号： C12Q1/6869 , B82Y5/00 , G01N33/48721 , Y10T436/143333
摘要： A technique for a nanodevice is provided. A reservoir is separated into two parts by a membrane. A nanopore is formed through the membrane, and the nanopore connects the two parts of the reservoir. The nanopore and the two parts of the reservoir are filled with ionic buffer. The membrane includes a graphene layer and insulating layers. The graphene layer is wired to first and second metal pads to form a graphene transistor in which transistor current flowing through the graphene transistor is modulated by charges or dipoles passing through the nanopore.
摘要翻译： 提供了一种纳米设备的技术。 通过膜将储存器分成两部分。 通过膜形成纳米孔，并且纳米孔连接储层的两个部分。 纳米孔和储存器的两个部分填充有离子缓冲液。 膜包括石墨烯层和绝缘层。 石墨烯层连接到第一和第二金属焊盘以形成石墨烯晶体管，其中流过石墨烯晶体管的晶体管电流通过电荷或穿过纳米孔的偶极子来调制。
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9.发明授权Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel 失效用于在V形通道的尖端处制造具有超薄SOI的器件的结构和方法公开(公告)号：US07528027B1
公开(公告)日：2009-05-05
申请号：US12054727
申请日：2008-03-25
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/82385 , H01L21/84 , H01L29/045 , H01L29/1037 , H01L29/66545 , H01L29/66621 , H01L29/66772
摘要： An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.
摘要翻译： SOI CMOS结构包括pFet区域中的v形沟槽。 V形沟槽具有（111）面中的表面并延伸到pFet区域中的SOI层。 在V形沟槽中形成诸如栅极氧化物或高k材料的层。 多晶硅沉积在层的顶部。
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![Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method](/abs-image/US/2009/03/17/US07504700B2/abs.jpg.150x150.jpg)
10.发明授权Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method 有权形成用于高性能CMOS应用的超薄[[HfSiO]]金属硅酸盐膜和在所述方法中形成的半导体结构的方法公开(公告)号：US07504700B2
公开(公告)日：2009-03-17
申请号：US10907935
申请日：2005-04-21
IPC分类号： H01L27/088 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28185 , H01L21/28097 , H01L21/28229 , H01L21/823857 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.
摘要翻译： 一种半导体结构及其制造方法，包括在基极电介质层的顶部形成扩散控制稳定材料的均匀缓冲层，然后形成含有过渡金属原子源的均匀层，然后退火 结构将过渡金属原子从其源极扩散通过扩散控制材料并进入基极栅极电介质层。
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