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公开(公告)号：US20110095783A1
公开(公告)日：2011-04-28
申请号：US12797557
申请日：2010-06-09
IPC分类号： H03K19/003
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。
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公开(公告)号：US08169233B2
公开(公告)日：2012-05-01
申请号：US12797557
申请日：2010-06-09
IPC分类号： H03K17/16 , H03K19/003 , G11C11/00
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。
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公开(公告)号：US20120206165A1
公开(公告)日：2012-08-16
申请号：US13455691
申请日：2012-04-25
IPC分类号： H03K19/003
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。
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4.发明授权Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween 有权在集成电路和电路板之间提供额外的空间，用于在其间定位组件公开(公告)号：US08080874B1
公开(公告)日：2011-12-20
申请号：US11855826
申请日：2007-09-14
申请人： Jeremy Werner , Daniel L. Rosenband , Jeremy Matthew Plunkett , William L. Schmidt , David T. Wang , Wael O. Zohni , Philip Arnold Ferolito , Michael John Sebastian Smith , Suresh Natarajan Rajan , Joseph C. Fjelstad
发明人： Jeremy Werner , Daniel L. Rosenband , Jeremy Matthew Plunkett , William L. Schmidt , David T. Wang , Wael O. Zohni , Philip Arnold Ferolito , Michael John Sebastian Smith , Suresh Natarajan Rajan , Joseph C. Fjelstad
CPC分类号： H05K1/181 , H01L23/13 , H01L23/3128 , H01L23/5387 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01087 , H01L2924/1203 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1304 , H01L2924/14 , H01L2924/1424 , H01L2924/1436 , H01L2924/15159 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/0281 , H05K1/141 , H05K1/147 , H05K2201/10454 , H05K2201/10484 , H05K2201/10515 , H05K2201/10522 , H05K2201/2018 , Y02P70/611 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system, method, and apparatus are included for providing additional space between an integrated circuit package and a circuit board. An integrated circuit package is provided including a plurality of integrated circuit package contacts. Also provided is a circuit board in electrical communication with the integrated circuit package. Further, the integrated circuit package, the integrated circuit contacts, and/or the circuit board is configured for providing additional space between the integrated circuit package and the circuit board to position at least a portion of at least one component between the integrated circuit package and the circuit board.
摘要翻译： 包括系统，方法和装置，用于在集成电路封装和电路板之间提供额外的空间。 提供了包括多个集成电路封装触点的集成电路封装。 还提供了与集成电路封装电通信的电路板。 此外，集成电路封装，集成电路触点和/或电路板被配置为在集成电路封装和电路板之间提供额外的空间，以将至少一部分的至少一部分置于集成电路封装和 电路板。
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公开(公告)号：US08710862B2
公开(公告)日：2014-04-29
申请号：US13455691
申请日：2012-04-25
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。
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公开(公告)号：US20130007399A1
公开(公告)日：2013-01-03
申请号：US13615008
申请日：2012-09-13
IPC分类号： G06F12/00
CPC分类号： G06F1/08
摘要： A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.
摘要翻译： 提供了一种用于调整与存储器系统相关联的信号的定时的系统和方法。 提供存储器控制器。 另外，提供至少一个存储器模块。 此外，提供至少一个接口电路，所述接口电路能够调整与所述存储器控制器和所述至少一个存储器模块中的一个或多个相关联的信号的定时。
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公开(公告)号：US08327104B2
公开(公告)日：2012-12-04
申请号：US11939440
申请日：2007-11-13
IPC分类号： G06F13/00
CPC分类号： G06F1/08
摘要： A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.
摘要翻译： 提供了一种用于调整与存储器系统相关联的信号的定时的系统和方法。 提供存储器控制器。 另外，提供至少一个存储器模块。 此外，提供至少一个接口电路，所述接口电路能够调整与所述存储器控制器和所述至少一个存储器模块中的一个或多个相关联的信号的定时。
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8.发明申请SYSTEM AND METHOD FOR ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM 有权用于调整与记忆系统相关的信号时序的系统和方法公开(公告)号：US20080115006A1
公开(公告)日：2008-05-15
申请号：US11939440
申请日：2007-11-13
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.
摘要翻译： 提供了一种用于调整与存储器系统相关联的信号的定时的系统和方法。 提供存储器控制器。 另外，提供至少一个存储器模块。 此外，提供至少一个接口电路，所述接口电路能够调整与所述存储器控制器和所述至少一个存储器模块中的一个或多个相关联的信号的定时。
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公开(公告)号：US08397013B1
公开(公告)日：2013-03-12
申请号：US12057306
申请日：2008-03-27
CPC分类号： G06F12/00 , G06F13/385 , G11C5/02 , G11C5/04 , G11C16/04 , G11C16/0483 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014
摘要： One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.
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公开(公告)号：US20120059976A1
公开(公告)日：2012-03-08
申请号：US12876393
申请日：2010-09-07
CPC分类号： G06F12/0253 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0246 , G06F2212/7205
摘要： A storage array controller provides a method and system for autonomously issuing trim commands to one or more solid-state storage devices in a storage array. The storage array controller is separate from any operating system running on a host system and separate from any controller in the solid-state storage device(s). The trim commands allow the solid-state storage device to operate more efficiently.
摘要翻译： 存储阵列控制器提供一种方法和系统，用于向存储阵列中的一个或多个固态存储设备自主地发出修剪命令。 存储阵列控制器与在主机系统上运行的任何操作系统分离，并与固态存储设备中的任何控制器分离。 修剪命令允许固态存储设备更有效地运行。
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