公开(公告)号：US20110095783A1

公开(公告)日：2011-04-28

申请号：US12797557

申请日：2010-06-09

申请人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Sebastian Smith

发明人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Sebastian Smith

IPC分类号： H03K19/003

CPC分类号： G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。

公开(公告)号：US08169233B2

公开(公告)日：2012-05-01

申请号：US12797557

申请日：2010-06-09

申请人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Sebastian Smith

发明人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Sebastian Smith

IPC分类号： H03K17/16 ,  H03K19/003 ,  G11C11/00

CPC分类号： G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。

公开(公告)号：US20120206165A1

公开(公告)日：2012-08-16

申请号：US13455691

申请日：2012-04-25

申请人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Sebastian Smith

发明人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Sebastian Smith

IPC分类号： H03K19/003

CPC分类号： G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。

公开(公告)号：US08080874B1

公开(公告)日：2011-12-20

申请号：US11855826

申请日：2007-09-14

申请人： Jeremy Werner ,  Daniel L. Rosenband ,  Jeremy Matthew Plunkett ,  William L. Schmidt ,  David T. Wang ,  Wael O. Zohni ,  Philip Arnold Ferolito ,  Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  Joseph C. Fjelstad

发明人： Jeremy Werner ,  Daniel L. Rosenband ,  Jeremy Matthew Plunkett ,  William L. Schmidt ,  David T. Wang ,  Wael O. Zohni ,  Philip Arnold Ferolito ,  Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  Joseph C. Fjelstad

IPC分类号： H01L23/34 ,  H01L23/48

CPC分类号： H05K1/181 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1424 ,  H01L2924/1436 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0281 ,  H05K1/141 ,  H05K1/147 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/2018 ,  Y02P70/611 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system, method, and apparatus are included for providing additional space between an integrated circuit package and a circuit board. An integrated circuit package is provided including a plurality of integrated circuit package contacts. Also provided is a circuit board in electrical communication with the integrated circuit package. Further, the integrated circuit package, the integrated circuit contacts, and/or the circuit board is configured for providing additional space between the integrated circuit package and the circuit board to position at least a portion of at least one component between the integrated circuit package and the circuit board.

摘要翻译： 包括系统，方法和装置，用于在集成电路封装和电路板之间提供额外的空间。 提供了包括多个集成电路封装触点的集成电路封装。 还提供了与集成电路封装电通信的电路板。 此外，集成电路封装，集成电路触点和/或电路板被配置为在集成电路封装和电路板之间提供额外的空间，以将至少一部分的至少一部分置于集成电路封装和 电路板。

公开(公告)号：US08710862B2

公开(公告)日：2014-04-29

申请号：US13455691

申请日：2012-04-25

申请人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Smith

发明人： Philip Arnold Ferolito ,  Daniel L. Rosenband ,  David T. Wang ,  Michael John Smith

IPC分类号： H03K17/16 ,  H03K19/003 ,  G11C7/10 ,  G11C8/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

摘要翻译： 提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。 提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。

公开(公告)号：US08279690B1

公开(公告)日：2012-10-02

申请号：US13367259

申请日：2012-02-06

申请人： Min Wang ,  Philip Arnold Ferolito ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith

发明人： Min Wang ,  Philip Arnold Ferolito ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith

IPC分类号： G11C7/00

CPC分类号： G06F13/4234 ,  G06F13/4086

摘要： A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

公开(公告)号：US08111566B1

公开(公告)日：2012-02-07

申请号：US11941589

申请日：2007-11-16

申请人： Min Wang ,  Philip Arnold Ferolito ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith

发明人： Min Wang ,  Philip Arnold Ferolito ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith

IPC分类号： G11C7/00

CPC分类号： G06F13/4234 ,  G06F13/4086

摘要： A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

摘要翻译： 提供了一种用于存储器控制器和多个存储器件之间的高速通信的系统。 提供存储器控制器和多个存储器件。 另外，包括至少一个通道以提供存储器控制器和多个存储器件之间的电气通信，使用高密度互连（HDI）技术至少部分地控制通道的阻抗。

公开(公告)号：US08675429B1

公开(公告)日：2014-03-18

申请号：US13597895

申请日：2012-08-29

申请人： Min Wang ,  Philip Arnold Ferolito ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith

发明人： Min Wang ,  Philip Arnold Ferolito ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith

IPC分类号： G11C7/00

CPC分类号： G06F13/4234 ,  G06F13/4086

摘要： A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

摘要翻译： 提供了一种用于存储器控制器和多个存储器件之间的高速通信的系统。 提供存储器控制器和多个存储器件。 另外，包括至少一个通道以提供存储器控制器和多个存储器件之间的电气通信，使用高密度互连（HDI）技术至少部分地控制通道的阻抗。

公开(公告)号：US5999531A

公开(公告)日：1999-12-07

申请号：US62377

申请日：1998-04-17

申请人： Philip Arnold Ferolito ,  Robert W. Pfile

发明人： Philip Arnold Ferolito ,  Robert W. Pfile

IPC分类号： H04L12/56 ,  H04J3/26

CPC分类号： H04L49/201 ,  H04L49/205 ,  H04L49/25 ,  H04L49/3009 ,  H04L49/3027

摘要： A method and apparatus for routing packets through a multiport switch involves attaching indicators to packets before the packets are passed through a switch fabric, and then using the indicators to look-up output port vectors after the packets have been passed through the switch fabric. In a preferred embodiment of a 64.times.64 port switch, an 8-bit output channel vector and a 15-bit output port index are attached to a packet and passed through the switch fabric. The 8-bit output channel vector directs the packet to the proper output packet processor(s) and the 15-bit output port index is used to look-up an output port vector that identifies the output port(s) that will receive the packet. The method and system provide low packet overhead and flexible scaling.

摘要翻译： 用于通过多端口交换机路由分组的方法和装置包括在分组通过交换结构之前将指示符附加到分组，然后在分组通过交换结构之后使用指示符来查找输出端口向量。 在64×64端口交换机的优选实施例中，8位输出通道向量和15位输出端口索引附加到数据包并通过交换结构。 8位输出通道向量将数据包引导到正确的输出数据包处理器，15位输出端口索引用于查找标识将接收数据包的输出端口的输出端口向量 。 该方法和系统提供低分组开销和灵活的缩放。

公开(公告)号：US6044061A

公开(公告)日：2000-03-28

申请号：US37218

申请日：1998-03-10

申请人： Gunes Aybay ,  Philip Arnold Ferolito

发明人： Gunes Aybay ,  Philip Arnold Ferolito

IPC分类号： H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/937 ,  H04L12/56

CPC分类号： H04L49/508 ,  H04L49/1576 ,  H04L49/203 ,  H04L49/254 ,  H04L49/352 ,  H04L49/608 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L49/201 ,  H04L49/30 ,  H04L49/40

摘要： An input-buffered multipoint switch having input channels and output channels includes multi-level request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multi-level request buffer associated with each input channel and each request buffer has multiple request registers for storing data cell transfer requests of different priorities. The multi-level request registers are linked in parallel to the scheduler to allow arbitration among requests of different input channels and different priority levels. The preferred arbitration process involves generating masks that reflect the output channels required by the same priority level requests. Utilizing masks to arbitrate between multiple requests in an input-buffered switch reduces arbitration cycle time and minimizes HOL blocking.

摘要翻译： 具有输入通道和输出通道的输入缓冲多点开关包括多级请求缓冲器，数据路径多路复用器和调度器。 交换机具有与每个输入通道相关联的不同的多级请求缓冲器，并且每个请求缓冲器具有用于存储不同优先级的数据单元传送请求的多个请求寄存器。 多级请求寄存器与调度器并行链接，以允许在不同输入通道的请求和不同优先级之间进行仲裁。 优选的仲裁过程涉及产生反映相同优先级请求所需的输出信道的掩码。 利用掩码在输入缓冲交换机中的多个请求之间进行仲裁可减少仲裁周期时间，并最大限度地减少HOL阻塞。