公开(公告)号：US09612970B2

公开(公告)日：2017-04-04

申请号：US14333981

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/12 ,  G06F12/10 ,  G06F12/0895

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

公开(公告)号：US09123408B2

公开(公告)日：2015-09-01

申请号：US13902705

申请日：2013-05-24

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。

公开(公告)号：US20160093345A1

公开(公告)日：2016-03-31

申请号：US14497902

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Michael Drop ,  Raghu Sankuratri

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1689

Abstract: A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold.

Abstract translation: 一种方法包括在控制器处检测要发送到第一时间的动态随机存取存储器（DRAM）的第一数据业务和第二时间发送到DRAM的第二数据业务之间的变化率。 该方法还包括响应于变化率满足阈值的确定来调整第二数据业务的数据速率。

公开(公告)号：US20160019158A1

公开(公告)日：2016-01-21

申请号：US14334010

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edward Turner ,  Jeong-Ho Woo

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0895 ,  G06F17/30902 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Abstract translation: 方面包括计算设备，系统和方法，用于通过集合和方式动态地将系统高速缓存分区到组件高速缓存中。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收系统高速缓存访​​问请求，并且在系统高速缓存中保留对应于与请求的组件高速缓存标识符相关联的组件高速缓存的位 在系统缓存中预留位置可以激活系统高速缓存中的位置以供请求客户端使用，并且还可以防止其他客户端使用系统高速缓存中的保留位置。 释放系统缓存中的位置可以停用系统缓存中的位置，并允许其他客户端使用它们。 保留系统缓存中的位置的客户端可以改变其在其组件高速缓存中保留的位置的数量。

公开(公告)号：US20150340078A1

公开(公告)日：2015-11-26

申请号：US14816820

申请日：2015-08-03

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C11/4076 ,  H03L7/093

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Abstract translation: 根据某些实施例提供了用于数据同步的方法。 该方法包括接收数据，数据时钟信号和清洁时钟信号，使用数据时钟信号对数据进行采样，使采样数据与干净的时钟信号同步，并输出同步的采样数据。 该方法还包括跟踪数据时钟信号和干净的时钟信号之间的相位漂移，以及如果跟踪的相位漂移在第一个时钟信号中达到第一个值，则将干扰时钟信号的同步采样数据的输出拉入一个时钟周期 方向。

公开(公告)号：US10089238B2

公开(公告)日：2018-10-02

申请号：US14334010

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edmund Turner ,  Jeong-Ho Woo

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F9/50 ,  G06F12/0888 ,  G06F12/0864 ,  G06F1/32 ,  G06F17/30

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

公开(公告)号：US09437278B2

公开(公告)日：2016-09-06

申请号：US14816820

申请日：2015-08-03

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Vijayalakshmi Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C11/4076 ,  H03L7/093 ,  G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Abstract translation: 根据某些实施例提供了用于数据同步的方法。 该方法包括接收数据，数据时钟信号和清洁时钟信号，使用数据时钟信号对数据进行采样，使采样数据与干净的时钟信号同步，并输出同步的采样数据。 该方法还包括跟踪数据时钟信号和干净的时钟信号之间的相位漂移，以及如果跟踪的相位漂移在第一个时钟信号中达到第一个值，则将干扰时钟信号的同步采样数据的输出拉入一个时钟周期 方向。

公开(公告)号：US09734070B2

公开(公告)日：2017-08-15

申请号：US14921468

申请日：2015-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： Alain Artieri ,  Subbarao Palacharla ,  Laurent Moll ,  Raghu Sankuratri ,  Kedar Bhole ,  Vinod Chamarty

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/0864 ,  G06F12/123

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

公开(公告)号：US20160019157A1

公开(公告)日：2016-01-21

申请号：US14333981

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract translation: 方面包括计算设备，系统和用于通过集合和方式将系统高速缓存分组到组件高速缓存中的方法。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收指定组件高速缓存标识符的系统高速缓存访​​问请求，并且将组件高速缓存标识符与组件高速缓存标识符的特征与组件高速缓存配置表相关联的记录进行匹配。 组件缓存特征可以包括设置的移动特征，设置偏移特征和目标方式，其可以定义系统高速缓存中的组件高速缓存的位置。 系统高速缓冲存储器控制器还可以在系统高速缓存访​​问请求中接收系统高速缓存的物理地址，确定组件高速缓存的索引模式，并转换组件高速缓存的物理地址。

公开(公告)号：US20140347941A1

公开(公告)日：2014-11-27

申请号：US13902705

申请日：2013-05-24

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。