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    Distributed differential interconnect
    1.
    发明授权
    Distributed differential interconnect 有权

    公开(公告)号：US10523272B2

    公开(公告)日：2019-12-31

    申请号：US15606820

    申请日：2017-05-26

    Applicant: QUALCOMM Incorporated

    Inventor： Madhukar Vallabhaneni ,  Girish Koppassery ,  Xinhua Chen ,  Jingcheng Zhuang

    IPC: H04B3/28 ,  H04L25/08 ,  H05K1/02 ,  H01R9/03 ,  H01R9/11 ,  H01R11/05 ,  H01R12/70 ,  H01R12/77 ,  H01R12/00 ,  H04L25/00 ,  H04L25/02

    Abstract: An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

    Fast coarse tuning for frequency synthesizer
    4.
    发明授权
    Fast coarse tuning for frequency synthesizer 有权

    公开(公告)号：US10715151B2

    公开(公告)日：2020-07-14

    申请号：US15933204

    申请日：2018-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： Yuehai Jin ,  Xinhua Chen

    IPC: H03L7/099 ,  H03L7/093 ,  H03M3/02 ,  H03K5/24 ,  H03M1/66 ,  H03K5/00 ,  H04L7/033 ,  H04L5/00

    Abstract: A coarse tuning synthesizer for wireless communication includes a digital control unit, a digital-to-analog converter, and a comparator. The digital control unit includes an output node coupled to a first input node of a VCO (voltage controlled oscillator). The digital-to-analog converter includes a first node coupled to the first input node of the VCO. The comparator includes an output node coupled to an input node of the digital control unit. The comparator also includes a first input node coupled to a second node of the digital-to-analog converter and a second input node coupled to an output node of the VCO.

    LOW POWER 25% DUTY CYCLE LOCAL OSCILLATOR CLOCK GENERATION CIRCUIT
    7.
    发明申请
    LOW POWER 25% DUTY CYCLE LOCAL OSCILLATOR CLOCK GENERATION CIRCUIT 审中-公开

    公开(公告)号：US20190181844A1

    公开(公告)日：2019-06-13

    申请号：US15835861

    申请日：2017-12-08

    Applicant: QUALCOMM Incorporated

    Inventor： Animesh Paul ,  Xinhua Chen

    IPC: H03K3/017 ,  H03K5/02

    Abstract: In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.

    PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING
    9.
    发明申请
    PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING 审中-公开
    使用双循环模式的相位锁定环来实现快速重置

    公开(公告)号：US20140241335A1

    公开(公告)日：2014-08-28

    申请号：US13780968

    申请日：2013-02-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xinhua Chen ,  Yiwu Tang

    IPC: H03L7/06

    CPC classification number: H03L7/0891 ,  H03L7/093 ,  H03L7/107

    Abstract: A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter. When the transmitter switches from a High Power mode (HP TX) to a Low Power mode (LP TX), the PLL is perturbed (VCO no longer generates the desired frequency) and must resettle within an allocated time. In one example, the VCO frequency is 3.96 GHz and the settling time requirement is 25 microseconds. Upon switching from HP TX to LP TX, the PLL is switched to the second high bandwidth mode 15 microseconds and is then switched back to the first low bandwidth mode. The PLL resettles to within 1 ppm of the initial VCO frequency of 3.96 GHz within the allocated 25 microseconds.

    Abstract translation: PLL使用第一控制环路在第一低带宽模式下工作，并且在第二高带宽模式中使用第二控制环路工作。 PLL包括VCO，其产生以发射机使用的期望频率的输出信号。 当发射机从高功率模式（HP TX）切换到低功耗模式（LP TX）时，PLL被扰乱（VCO不再产生所需频率），并且必须在分配的时间内重新定位。 在一个示例中，VCO频率为3.96GHz，建立时间要求为25微秒。 从HP TX切换到LP TX时，PLL将切换到第二个高带宽模式15微秒，然后切换回第一个低带宽模式。 PLL在分配的25微秒内重置到3.96 GHz的初始VCO频率的1 ppm以内。

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