专利检索 cpc:"H01L2224/0905" 第 1 页

1.

发明申请
SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件

公开(公告)号：US20160093589A1

公开(公告)日：2016-03-31

申请号：US14863837

申请日：2015-09-24

申请人： Renesas Electronics Corporation

发明人： Yukihiro SATO , Katsuhiko FUNATSU , Takamitsu KANAZAWA , Masahiro KOIDO , Hiroyoshi TAYA

IPC分类号： H01L25/065 , H01L23/00

CPC分类号： H01L25/0655 , H01L21/4846 , H01L23/049 , H01L23/24 , H01L23/3735 , H01L23/49838 , H01L23/49844 , H01L23/49861 , H01L24/09 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L25/16 , H01L25/18 , H01L2224/0603 , H01L2224/0905 , H01L2224/32225 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48227 , H01L2224/4846 , H01L2224/48472 , H01L2224/49111 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2924/13055 , H01L2924/13091 , H01L2924/16151 , H01L2924/16251 , H01L2924/181 , H02M7/219 , H01L2924/00012 , H01L2924/00 , H01L2924/00014

摘要： Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

摘要翻译： 抑制半导体器件的可靠性降低。半导体器件包括形成在陶瓷衬底上的多个金属图案和安装在多个金属图案上的多个半导体芯片。此外，多个金属图案包括彼此面对的金属图案MPH和MPU。此外，设置在这些金属图案MPH和MPU之间并且从多个金属图案露出的区域沿着金属图案MPH的延伸方向延伸成锯齿状。

2.

发明申请
STRESS-RESILIENT CHIP STRUCTURE AND DICING PROCESS 审中-公开
标题翻译：应力弹性芯片结构和定位过程

公开(公告)号：US20150001714A1

公开(公告)日：2015-01-01

申请号：US14485207

申请日：2014-09-12

申请人： International Business Machines Corporation , DISCO Corporation

发明人： Richard F. Indyk , Ian D. Melville , Shigefumi Okada

IPC分类号： H01L23/00

CPC分类号： H01L24/09 , H01L21/561 , H01L21/78 , H01L21/782 , H01L23/492 , H01L23/562 , H01L24/17 , H01L24/94 , H01L24/95 , H01L2224/0401 , H01L2224/0901 , H01L2224/0905 , H01L2224/16225 , H01L2224/17104 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/014 , H01L2924/12042 , H01L2924/00012 , H01L2924/00 , H01L2224/11

摘要： A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

摘要翻译： 衬底包括以栅格图案排列并且通过沟道区彼此横向间隔开的多个半导体芯片。衬底包括半导体层的垂直堆叠和嵌入金属互连结构的至少一个电介质材料层。所述至少一个介电材料层沿着沟道区域和栅格图案的顶点被去除，使得每个半导体芯片包括不平行于栅格图案的角的角面。角面可以包括直的表面或凸面。半导体芯片被切割并随后结合到使用底部填充材料的封装衬底上。拐角表面减少在接合过程和随后的热循环过程中施加到金属互连层的机械应力。

3.

发明授权
Wafer level package (WLP) ball support using cavity structure 有权

公开(公告)号：US10074625B2

公开(公告)日：2018-09-11

申请号：US14859323

申请日：2015-09-20

申请人： QUALCOMM Incorporated

发明人： Mario Francisco Velez , David Francis Berdy , Changhan Hobie Yun , Jonghae Kim , Chengjie Zuo , Daeik Daniel Kim , Je-Hsiung Jeffrey Lan , Niranjan Sunil Mudakatte , Robert Paul Mikulka

IPC分类号： H01L23/00 , H01L23/13 , H01L23/498

CPC分类号： H01L24/17 , H01L23/13 , H01L23/49816 , H01L24/03 , H01L24/09 , H01L24/11 , H01L2224/023 , H01L2224/0905

摘要： An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.

4.

发明申请
Fan-out 3D IC Integration Structure without Substrate and Method of Making the Same 有权

公开(公告)号：US20170117251A1

公开(公告)日：2017-04-27

申请号：US14954679

申请日：2015-11-30

申请人： Broadcom Corporation

发明人： Rezaur Rahman KHAN , Sam Ziqun ZHAO

IPC分类号： H01L25/065 , H01L23/528 , H01L23/00 , H01L23/50 , H01L23/31 , H01L23/48

CPC分类号： H01L25/0652 , H01L23/3107 , H01L23/3135 , H01L23/481 , H01L23/50 , H01L23/528 , H01L24/09 , H01L24/17 , H01L25/0657 , H01L2224/0905 , H01L2224/13014 , H01L2224/13016 , H01L2224/16145 , H01L2225/06513 , H01L2225/06548 , H01L2225/06589

摘要： A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.

5.

发明授权
Substrate with electrically isolated bond pads 有权
标题翻译：基片与电隔离接合垫

公开(公告)号：US09209144B1

公开(公告)日：2015-12-08

申请号：US14499264

申请日：2014-09-29

申请人： Lee Fee Ngion , Zi Song Poh

发明人： Lee Fee Ngion , Zi Song Poh

IPC分类号： H01L23/49 , H01L23/00 , H01L23/498 , H01L23/14 , H01L21/78 , H01L21/48

CPC分类号： H01L24/09 , H01L21/4889 , H01L21/78 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/92 , H01L24/97 , H01L2224/05014 , H01L2224/05554 , H01L2224/0612 , H01L2224/0905 , H01L2224/0951 , H01L2224/48091 , H01L2224/48227 , H01L2224/4911 , H01L2224/49113 , H01L2224/92247 , H01L2924/00014 , H01L2924/10162 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599

摘要： A substrate for use in semiconductor device assembly has an electrically insulating body with a die mounting surface and an opposite grid array surface. An array of external electrical connection pads is located in the grid array surface. Substrate bond padsare located in the die mounting surface. Interconnects in the insulating body selectively interconnect the substrate bond padsto the external electrical connection pads. Tertiary bond pads are located in the die mounting surface and are electrically isolated from the external electrical connection pads.

摘要翻译： 用于半导体器件组件的衬底具有电绝缘体，其具有管芯安装表面和相对的栅极阵列表面。外部电连接焊盘的阵列位于网格阵列表面中。衬底焊盘位于模具安装表面。绝缘体中的互连选择性地将衬底接合焊盘互连到外部电连接焊盘。三次接合焊盘位于管芯安装表面，并与外部电连接焊盘电隔离。

6.

发明授权
Fan-out 3D IC integration structure without substrate and method of making the same 有权

公开(公告)号：US09837378B2

公开(公告)日：2017-12-05

申请号：US14954679

申请日：2015-11-30

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Rezaur Rahman Khan , Sam Ziqun Zhao

IPC分类号： H01L25/065 , H01L23/31 , H01L23/48 , H01L23/50 , H01L23/528 , H01L23/00

CPC分类号： H01L25/0652 , H01L23/3107 , H01L23/3135 , H01L23/481 , H01L23/50 , H01L23/528 , H01L24/09 , H01L24/17 , H01L25/0657 , H01L2224/0905 , H01L2224/13014 , H01L2224/13016 , H01L2224/16145 , H01L2225/06513 , H01L2225/06548 , H01L2225/06589

摘要： A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.

7.

发明申请
Semiconductor Packages and Methods of Forming the Same 审中-公开

公开(公告)号：US20160233203A1

公开(公告)日：2016-08-11

申请号：US15131821

申请日：2016-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen , Jie Chen

IPC分类号： H01L25/00 , H01L21/48 , H01L21/56

CPC分类号： H01L25/50 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L23/3107 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/96 , H01L25/065 , H01L25/105 , H01L2221/68327 , H01L2221/68345 , H01L2221/68372 , H01L2224/02331 , H01L2224/02373 , H01L2224/03003 , H01L2224/0401 , H01L2224/04105 , H01L2224/05082 , H01L2224/05083 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/0905 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/12105 , H01L2224/13008 , H01L2224/13021 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13181 , H01L2224/13294 , H01L2224/133 , H01L2224/13311 , H01L2224/16227 , H01L2224/17181 , H01L2224/2518 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/81005 , H01L2224/81024 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81447 , H01L2224/81815 , H01L2224/81895 , H01L2224/92 , H01L2224/96 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2924/3511 , H01L2224/45099 , H01L2924/00 , H01L2224/81 , H01L2924/01029 , H01L2924/0105 , H01L2924/014 , H01L2924/01047 , H01L2221/68304 , H01L21/304 , H01L2221/68381 , H01L2224/03 , H01L2924/01074 , H01L2224/05655 , H01L2924/00011 , H01L2924/00012

摘要： Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

8.

发明申请
SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME 有权
标题翻译：半导体封装及其形成方法

公开(公告)号：US20150270232A1

公开(公告)日：2015-09-24

申请号：US14222475

申请日：2014-03-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen , Jie Chen

IPC分类号： H01L23/00 , H01L21/56 , H01L23/31

CPC分类号： H01L25/50 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L23/3107 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/96 , H01L25/065 , H01L25/105 , H01L2221/68327 , H01L2221/68345 , H01L2221/68372 , H01L2224/02331 , H01L2224/02373 , H01L2224/03003 , H01L2224/0401 , H01L2224/04105 , H01L2224/05082 , H01L2224/05083 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/0905 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/12105 , H01L2224/13008 , H01L2224/13021 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13181 , H01L2224/13294 , H01L2224/133 , H01L2224/13311 , H01L2224/16227 , H01L2224/17181 , H01L2224/2518 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/81005 , H01L2224/81024 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81447 , H01L2224/81815 , H01L2224/81895 , H01L2224/92 , H01L2224/96 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2924/3511 , H01L2224/45099 , H01L2924/00 , H01L2224/81 , H01L2924/01029 , H01L2924/0105 , H01L2924/014 , H01L2924/01047 , H01L2221/68304 , H01L21/304 , H01L2221/68381 , H01L2224/03 , H01L2924/01074 , H01L2224/05655 , H01L2924/00011 , H01L2924/00012

摘要： Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

摘要翻译： 本公开的实施例包括半导体封装及其形成方法。一个实施例是一种半导体封装，其包括包括一个或多个管芯的第一封装，以及在第一封装的第一侧处与第一组接合接头耦合到一个或多个管芯的再分配层。再分配层包括设置在多于一个钝化层中的多于一个金属层，第一组接合接头直接耦合到一个或多个金属层中的至少一个，以及耦合到第一组连接器再分配层，第二侧与第一侧相对。

9.

发明申请
STRESS-RESILIENT CHIP STRUCTURE AND DICING PROCESS 审中-公开
标题翻译：应力弹性芯片结构和定位过程

公开(公告)号：US20140151879A1

公开(公告)日：2014-06-05

申请号：US13689805

申请日：2012-11-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DISCO CORPORATION

发明人： Richard F. Indyk , Ian D. Melville , Shigefumi Okada

IPC分类号： H01L21/782 , H01L23/492

CPC分类号： H01L24/09 , H01L21/561 , H01L21/78 , H01L21/782 , H01L23/492 , H01L23/562 , H01L24/17 , H01L24/94 , H01L24/95 , H01L2224/0401 , H01L2224/0901 , H01L2224/0905 , H01L2224/16225 , H01L2224/17104 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/014 , H01L2924/12042 , H01L2924/00012 , H01L2924/00 , H01L2224/11

摘要： A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

摘要翻译： 衬底包括以栅格图案排列并且通过沟道区彼此横向间隔开的多个半导体芯片。衬底包括半导体层的垂直堆叠和嵌入金属互连结构的至少一个电介质材料层。所述至少一个介电材料层沿着沟道区域和栅格图案的顶点被去除，使得每个半导体芯片包括不平行于栅格图案的角的角面。角面可以包括直的表面或凸面。半导体芯片被切割并随后结合到使用底部填充材料的封装衬底上。拐角表面减少在接合过程和随后的热循环过程中施加到金属互连层的机械应力。