公开(公告)号：US20240305296A1

公开(公告)日：2024-09-12

申请号：US18181026

申请日：2023-03-09

Applicant: QUALCOMM Incorporated

Inventor： Lei SUN ,  Elias DAGHER ,  Dinesh Jagannath ALLADI

IPC: H03K19/003 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017

CPC classification number: H03K19/00361 ,  H03K17/063 ,  H03K17/6871 ,  H03K19/01735

Abstract: A system includes a switch transistor, and a bootstrap circuit having an input and an output, wherein the output of the bootstrap circuit is coupled to a gate of the switch transistor. The system also includes a first buffer having an input and an output, wherein the output of the first buffer is coupled to a terminal of the switch transistor. The system further includes a second buffer having an input and an output, wherein the input of the second buffer is coupled to the input of the first buffer, and the output of the second buffer is coupled to the input of the bootstrap circuit.

公开(公告)号：US20190334539A1

公开(公告)日：2019-10-31

申请号：US15962967

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Timothy Donald GATHMAN ,  Yuhua GUO ,  Lai Kan LEUNG ,  Elias DAGHER ,  Dinesh Jagannath ALLADI

IPC: H03M1/12 ,  H04B1/16

Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

公开(公告)号：US20240167889A1

公开(公告)日：2024-05-23

申请号：US17989614

申请日：2022-11-17

Applicant: QUALCOMM Incorporated

Inventor： Balasubramanian SIVAKUMAR ,  Liang DAI ,  Dinesh Jagannath ALLADI

IPC: G01K7/01

CPC classification number: G01K7/01

Abstract: A subthreshold-based MOSFET temperature sensor is provided for generating a subthreshold leakage current that is proportional to a difference between a gate-to-source voltage of a first transistor and a gate-to-source voltage of a second transistor. The subthreshold leakage current is mirrored to a detector for a temperature determination.

公开(公告)号：US20230253400A1

公开(公告)日：2023-08-10

申请号：US17650233

申请日：2022-02-07

Applicant: QUALCOMM Incorporated

Inventor： Bruce LEE ,  Chandra Satya Priyanka TIRUPATHI ,  Liang DAI ,  Dinesh Jagannath ALLADI

IPC: H01L27/07 ,  H01L27/08

CPC classification number: H01L27/0733 ,  H01L27/0805

Abstract: A device includes a first plurality of MEOL interconnects coupled to a second node that extends in a first direction. The first plurality of MEOL interconnects includes first and second subsets of MEOL second-terminal interconnects. The device includes a second plurality of MEOL interconnects coupled to a first node that extends in the first direction. The second plurality of MEOL interconnects includes first and second subsets of MEOL first-terminal interconnects. The first subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a first subset of interleaved MEOL interconnects. The second subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a second subset of interleaved MEOL interconnects. The device includes at least one of a first plurality of gate interconnects or a first plurality of OD regions extending in a second direction orthogonal to the first direction between the first and second subsets of interleaved MEOL interconnects.

公开(公告)号：US20240195297A1

公开(公告)日：2024-06-13

申请号：US18080607

申请日：2022-12-13

Applicant: QUALCOMM Incorporated

Inventor： Xiaopeng ZHONG ,  Dinesh Jagannath ALLADI

IPC: H02M3/155 ,  H02M1/08 ,  H02M1/32 ,  H04B1/40

CPC classification number: H02M3/155 ,  H02M1/08 ,  H02M1/32 ,  H04B1/40

Abstract: An apparatus including: a boost voltage generator configured to generate a boost voltage at an output; a first field effect transistor (FET) including a drain/source terminal coupled to the output of the boost voltage generator; a discharging circuit coupled to a source/drain terminal of the first FET, wherein the discharging circuit is configured to discharge the output of the boost voltage generator via the first FET in response to an asserted discharging signal; and a gate voltage boost circuit configured to generate a gate voltage for a gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to the asserted discharging signal. Another implementation may include a current injection circuit configured to generate and inject a current into the discharging circuit in lieu of or in addition to the gate voltage boost circuit.

公开(公告)号：US20220311460A1

公开(公告)日：2022-09-29

申请号：US17211769

申请日：2021-03-24

Applicant: QUALCOMM Incorporated

Inventor： Meysam AZIN ,  Li LU ,  Anees HABIB ,  Chinmaya MISHRA ,  Damin CAO ,  Arul BALASUBRAMANIYAN ,  David Ta-hsiang LIN ,  Shuang ZHU ,  Dinesh Jagannath ALLADI

IPC: H04B1/04 ,  H03M1/46 ,  H03M3/00

Abstract: Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

公开(公告)号：US20160261277A1

公开(公告)日：2016-09-08

申请号：US14639534

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yan WANG ,  Dinesh Jagannath ALLADI ,  Chieh-Yu HSIEH ,  Elias Hani DAGHER

IPC: H03M3/00

CPC classification number: H03M3/32 ,  H03M3/354 ,  H03M3/392 ,  H03M3/45 ,  H03M3/454 ,  H03M3/496

Abstract: A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Abstract translation: 提供了一种用于分离Δ-Σ调制器的开关电容积分器的方法和装置。 该装置配置第一积分器和第二积分器以彼此并联耦合，在第一模式和第二模式之间切换使得第一积分器能够对输入信号进行操作，以在第一模式中产生输出信号，以及 使第一积分器和第二积分器在第二模式下对输入信号协同工作，其中在第二模式中，该装置经由第一积分器产生第一输出，经由第二积分器产生第二输出，并且收敛第一 输出与第二个输出端产生输出信号。

公开(公告)号：US20230387929A1

公开(公告)日：2023-11-30

申请号：US17804779

申请日：2022-05-31

Applicant: QUALCOMM Incorporated

Inventor： Behnam SEDIGHI ,  Shi BU ,  Elias DAGHER ,  Dinesh Jagannath ALLADI

IPC: H03M1/08

CPC classification number: H03M1/0854

Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.

公开(公告)号：US20200333819A1

公开(公告)日：2020-10-22

申请号：US16835494

申请日：2020-03-31

Applicant: QUALCOMM Incorporated

Inventor： Balasubramanian SIVAKUMAR ,  Dinesh Jagannath ALLADI ,  Kentaro YAMAMOTO ,  Sean BAKER ,  Liang ZHAO

IPC: G05F3/08

Abstract: An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

公开(公告)号：US20180241409A1

公开(公告)日：2018-08-23

申请号：US15440612

申请日：2017-02-23

Applicant: QUALCOMM Incorporated

Inventor： Elias DAGHER ,  Yan WANG ,  Mohammad Meysam ZARGHAM ,  Dinesh Jagannath ALLADI

IPC: H03M1/12 ,  H03M3/00

CPC classification number: H03M1/1245 ,  H03M3/37 ,  H03M3/396 ,  H03M3/458 ,  H03M3/464

Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.