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    Dynamic memory protection
    2.
    发明授权
    Dynamic memory protection 有权

    公开(公告)号：US10740017B2

    公开(公告)日：2020-08-11

    申请号：US15963668

    申请日：2018-04-26

    申请人： QUALCOMM Incorporated

    发明人： Chando Park ,  Wei-Chuan Chen ,  Sungryul Kim ,  Adam Edward Newham ,  Seung Hyuk Kang ,  Rashid Ahmed Akbar Attar

    IPC分类号： G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372 ,  H04W4/80

    摘要： Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

    Smart battery wear leveling for audio devices
    3.
    发明授权
    Smart battery wear leveling for audio devices 有权

    公开(公告)号：US10701629B2

    公开(公告)日：2020-06-30

    申请号：US16274637

    申请日：2019-02-13

    申请人： QUALCOMM Incorporated

    发明人： Adam Edward Newham

    IPC分类号： H04W52/02 ,  H04R1/10

    摘要： Various embodiments provide systems and methods among wireless earpieces in a wireless communication network that enable balancing the batteries in the wireless earpieces to be depleted at approximately the same rate. Various embodiments intelligently and dynamically swap master/slave roles among two or more Bluetooth® wireless earpieces coupled to a data source device to optimize battery life in both wireless earpieces. The various embodiments provide methods and systems for swapping master-slave roles so that there is less impact on the user experience.

    Wireless connecting mobile devices and wearable devices
    4.
    发明授权
    Wireless connecting mobile devices and wearable devices 有权
    无线连接移动设备和可穿戴设备

    公开(公告)号：US09100944B2

    公开(公告)日：2015-08-04

    申请号：US14153676

    申请日：2014-01-13

    申请人： QUALCOMM Incorporated

    发明人： Adam Edward Newham ,  Nikhil Jain ,  Rohit Sauhta ,  Praveen Kumar Yaramada ,  Karthik Chitireddy

    IPC分类号： H04W4/00 ,  H04W76/02 ,  H04W52/02

    CPC分类号： H04W76/023 ,  H04M1/7253 ,  H04M1/72558 ,  H04M19/04 ,  H04W4/80 ,  H04W52/0251 ,  H04W76/14 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/162 ,  Y02D70/164 ,  Y02D70/26

    摘要： The various aspects provide for wirelessly connecting mobile devices and wearable devices, which may enhance battery life and user experience. The embodiments may determine whether the mobile device is streaming audio data to a wirelessly connected peripheral audio device. Requests from the mobile device to wirelessly connect to the wearable device may be deferred while the mobile device is streaming audio data to the peripheral audio device using the same communication protocol as the wireless connection to be made between the mobile device and the wearable device. The mobile device may determine when streaming of audio data to the peripheral audio device has stopped. The mobile device may send a request to wirelessly connect to the wearable device when the mobile device is not streaming audio data to the peripheral audio device using the same communication protocol.

    摘要翻译： 各种方面提供无线连接移动设备和可穿戴设备，这可以增强电池寿命和用户体验。 实施例可以确定移动设备是否将音频数据流传输到无线连接的外围音频设备。 当移动设备使用与在移动设备和可穿戴设备之间进行的无线连接相同的通信协议将音频数据流传输到外围音频设备时，可能推迟从移动设备到无线连接到可穿戴设备的请求。 移动设备可以确定音频数据到外围音频设备何时流动已停止。 当移动设备不使用相同的通信协议将音频数据流传输到外围音频设备时，移动设备可以发送无线连接到可穿戴设备的请求。

    Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems
    7.
    发明授权
    Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems 有权

    公开(公告)号：US09753874B2

    公开(公告)日：2017-09-05

    申请号：US14627318

    申请日：2015-02-20

    申请人： QUALCOMM Incorporated

    发明人： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

    IPC分类号： G06F13/28 ,  G06F12/02 ,  G06F9/44

    CPC分类号： G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

    摘要： Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

    MULTI-STEP PROGRAMMING OF HEAT-SENSITIVE NON-VOLATILE MEMORY (NVM) IN PROCESSOR-BASED SYSTEMS
    8.
    发明申请
    MULTI-STEP PROGRAMMING OF HEAT-SENSITIVE NON-VOLATILE MEMORY (NVM) IN PROCESSOR-BASED SYSTEMS 有权
    基于处理器的系统中的高可靠性非易失性存储器（NVM）的多级编程

    公开(公告)号：US20160246608A1

    公开(公告)日：2016-08-25

    申请号：US14627318

    申请日：2015-02-20

    申请人： QUALCOMM Incorporated

    发明人： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

    IPC分类号： G06F9/44 ,  G06F13/28 ,  G06F12/02

    CPC分类号： G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

    摘要： Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

    摘要翻译： 公开了基于处理器的系统中的热敏非易失性存储器（NVM）的多步编程以及相关的方法和系统。 为了避免在制造期间依赖于存储在热敏NVM中的编程指令，其中编程指令可能在热封装过程中被破坏，NVM以多步编程过程编程。 在第一编程步骤中，包括编程指令的引导加载器被加载到NVM中。 引导加载程序可能在打包完成后的热处理后加载到NVM中，以避免引导加载程序中的数据损坏风险。 此后，与使用较低传输速率编程技术加载编程图像相比，编程图像可以使用引导加载程序通过外设接口快速加载到NV程序存储器中，从而节省编程时间和相关成本。 处理器可以执行程序指令以在基于处理器的系统中执行任务。

    Ultra-low-power design memory power reduction scheme
    9.
    发明授权
    Ultra-low-power design memory power reduction scheme 有权

    公开(公告)号：US10539997B2

    公开(公告)日：2020-01-21

    申请号：US15255176

    申请日：2016-09-02

    申请人： QUALCOMM Incorporated

    发明人： Giby Samson ,  Parixit Laljibhai Aghera ,  Adam Edward Newham

    IPC分类号： G06F1/32 ,  G06F1/3287 ,  G06F1/3296

    摘要： The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.