公开(公告)号：US20180292875A1

公开(公告)日：2018-10-11

申请号：US15484669

申请日：2017-04-11

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Manisha Singh ,  Vinay Jain ,  Venkata Devarasetty

IPC: G06F1/26 ,  G06F13/24 ,  G06F1/32 ,  G06F1/30

CPC classification number: G06F1/266 ,  G06F1/305 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/4812 ,  G06F13/24

Abstract: Aspects of the disclosure are directed to DC power management. A sequencer may be configured to execute a first command, wherein the first command is associated with a unique group tag; compare the unique group tag to a master group tag; determine if an interrupt is detected; lock the master group tag to yield a locked master group tag; execute a second command, wherein the second command is associated with the locked master group tag; determine that an end of commands in the locked master group tag is reached and execute a sequence jump through command to put a processor back to a regular power state.

公开(公告)号：US10338655B2

公开(公告)日：2019-07-02

申请号：US15484669

申请日：2017-04-11

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Manisha Singh ,  Vinay Jain ,  Venkata Devarasetty

IPC: G06F1/00 ,  G06F1/26 ,  G06F13/24 ,  G06F1/3287 ,  G06F1/30 ,  G06F9/38 ,  G06F1/3203 ,  G06F1/3206 ,  G06F9/48

Abstract: Aspects of the disclosure are directed to DC power management. A sequencer may be configured to execute a first command, wherein the first command is associated with a unique group tag; compare the unique group tag to a master group tag; determine if an interrupt is detected; lock the master group tag to yield a locked master group tag; execute a second command, wherein the second command is associated with the locked master group tag; determine that an end of commands in the locked master group tag is reached and execute a sequence jump through command to put a processor back to a regular power state.

公开(公告)号：US20170364140A1

公开(公告)日：2017-12-21

申请号：US15187426

申请日：2016-06-20

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Pawan Chhabra ,  Navid Toosizadeh ,  Sreekanth Nallagatla ,  Shih-Hsin Jason Hu

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324

Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.

公开(公告)号：US10359833B2

公开(公告)日：2019-07-23

申请号：US15187426

申请日：2016-06-20

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Pawan Chhabra ,  Navid Toosizadeh ,  Sreekanth Nallagatla ,  Shih-Hsin Jason Hu

IPC: G06F1/3206 ,  G06F1/3296 ,  G06F1/08 ,  G06F1/3228 ,  G06F1/324

Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.

公开(公告)号：US09886081B2

公开(公告)日：2018-02-06

申请号：US15010237

申请日：2016-01-29

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Rakesh Misra

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: An apparatus includes a first circuit configured to receive one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The first circuit further selects one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes. A second circuit is configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores.