公开(公告)号：US20180341603A1

公开(公告)日：2018-11-29

申请号：US15992112

申请日：2018-05-29

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/32 ,  G06F12/02

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US11200181B2

公开(公告)日：2021-12-14

申请号：US16828570

申请日：2020-03-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F1/3234 ,  G06F12/02

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US12189548B2

公开(公告)日：2025-01-07

申请号：US17534180

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US20170249265A1

公开(公告)日：2017-08-31

申请号：US15458166

申请日：2017-03-14

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

公开(公告)号：US20150019786A1

公开(公告)日：2015-01-15

申请号：US14284473

申请日：2014-05-22

Applicant: RAMBUS INC.

Inventor： Arun Vaidyanath ,  Craig E. Hampel

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F13/16 ,  G06F12/06 ,  G06F13/1689 ,  G06F2212/251 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/023 ,  G11C29/025 ,  G11C29/027

Abstract: A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time.

Abstract translation: 存储器系统包括还包括一组存储器件的存储器模块。 该组存储器件包括存储器件的第一子集和存储器件的第二子集。 地址总线设置在存储器模块上，其中地址总线包括耦合到第一子集的第一段和耦合到第二子集的第二段。 地址信号依次遍历该组存储器件。 存储器系统还包括耦合到存储器模块的存储器控​​制器。 存储器控制器包括第一电路，用于输出控制第一子集的第一控制信号，使得第一控制信号和地址信号在基本上同时到达第一子集中的存储器件。 存储器控制器还包括第二电路，用于输出控制第二子集的第二控制信号，使得第二控制信号和地址信号在基本上同时到达第二子集中的存储器件。

公开(公告)号：US09996485B2

公开(公告)日：2018-06-12

申请号：US15458166

申请日：2017-03-14

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

公开(公告)号：US09298228B1

公开(公告)日：2016-03-29

申请号：US14810410

申请日：2015-07-27

Applicant: Rambus Inc.

Inventor： Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  Thomas J. Giovannini ,  Ming Li ,  David A. Secker ,  Arun Vaidyanath ,  Donald R. Mullen ,  Adrian F. Torres

IPC: H05K1/11 ,  H05K1/14 ,  G06F1/18

CPC classification number: G06F1/185

Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.

Abstract translation: 具有存储器提升子子系统的计算系统。 计算系统包括具有存储器模块连接器的主板和插入到第一存储器模块连接器中的转接卡。 第一个夹层卡连接到转接卡。 第一夹层卡包括用于第一存储器模块的第一夹层存储器模块连接器和用于第二存储器模块的第二夹层存储器模块连接器。 存储通道经由主板，第一转接卡和第一夹层卡将存储器控制器电连接到第一夹层存储器模块连接器和第二夹层模块连接器。 存储器通道可以被分成连接到第一夹层存储器模块连接器的第一数据子通道和连接到第二夹层存储器模块连接器的第二数据子通道。

公开(公告)号：US20150310903A1

公开(公告)日：2015-10-29

申请号：US14687739

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

公开(公告)号：US20250156348A1

公开(公告)日：2025-05-15

申请号：US18959973

申请日：2024-11-26

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US20220147472A1

公开(公告)日：2022-05-12

申请号：US17534180

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.