中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.015 seconds)

    Techniques for phase detection
    1.
    发明授权
    Techniques for phase detection 有权
    相位检测技术

    公开(公告)号：US09083280B2

    公开(公告)日：2015-07-14

    申请号：US14452187

    申请日：2014-08-05

    Applicant: Rambus Inc.

    Inventor： Brian Leibowitz ,  Hae-Chang Lee ,  Farshid Aryanfar ,  Kun-Yung Chang ,  Jie Shen

    IPC: H03D13/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/085

    CPC classification number: H03D13/00 ,  H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

    Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

    Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于相位对齐的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

    Signal Distribution Networks and Related Methods
    3.
    发明申请
    Signal Distribution Networks and Related Methods 有权
    信号分配网络及相关方法

    公开(公告)号：US20140333356A1

    公开(公告)日：2014-11-13

    申请号：US14089094

    申请日：2013-11-25

    Applicant: Rambus Inc.

    Inventor： Farshid Aryanfar ,  Hae-Chang Lee ,  Kun-Yung Chang ,  Ting Wu ,  Carl Werner ,  Masoud Koochakzadeh

    IPC: H03L7/093 ,  H03L7/08

    CPC classification number: H03L7/093 ,  G06F1/10 ,  H03L7/0802

    Abstract: A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

    Abstract translation: 信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过 传输线。 可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。 信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。 相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。 谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。

    COLLABORATIVE CHANNEL SOUNDING IN MULTI-ANTENNA SYSTEMS
    4.
    发明申请
    COLLABORATIVE CHANNEL SOUNDING IN MULTI-ANTENNA SYSTEMS 有权
    多天线系统中的协同通道声音

    公开(公告)号：US20140323054A1

    公开(公告)日：2014-10-30

    申请号：US14364002

    申请日：2012-12-20

    Applicant: RAMBUS INC.

    Inventor： Farshid Aryanfar ,  Carl W. Werner ,  Aykut Bultan

    IPC: H04B7/005

    CPC classification number: H04B7/005 ,  H04L25/0204

    Abstract: The disclosed embodiments relate to a system that performs channel-sounding operations in a multi-antenna wireless communication system. During operation, the system first performs channel-sounding operations between a first client and a second client in a first frequency band. These channel-sounding operations involve transmitting a series of known tones between the first client and the second client and using signals received as a result of the transmissions to finds a strongest path between the first client and the second client. Next, the system uses the identified strongest path to improve channel-sounding operations in a second frequency band.

    Abstract translation: 所公开的实施例涉及在多天线无线通信系统中执行信道探测操作的系统。 在操作期间，系统首先在第一频带中在第一客户端和第二客户端之间执行信道探测操作。 这些信道探测操作涉及在第一客户机和第二客户端之间传送一系列已知的音调，并使用作为传输结果而接收的信号，以在第一客户机和第二客户机之间找到最强的路径。 接下来，系统使用所识别的最强路径来改善第二频带中的频道探测操作。

    Wide range frequency synthesizer with quadrature generation and spur cancellation
    5.
    发明授权
    Wide range frequency synthesizer with quadrature generation and spur cancellation 有权

    公开(公告)号：US10587276B2

    公开(公告)日：2020-03-10

    申请号：US16382580

    申请日：2019-04-12

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Farshid Aryanfar

    IPC: H03L7/06 ,  H03L7/23 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18

    Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

    Wide range frequency synthesizer with quadrature generation and spur cancellation
    8.
    发明授权
    Wide range frequency synthesizer with quadrature generation and spur cancellation 有权

    公开(公告)号：US10298244B2

    公开(公告)日：2019-05-21

    申请号：US15605932

    申请日：2017-05-25

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Farshid Aryanfar

    IPC: H03L7/06 ,  H03L7/23 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18

    Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Patent Agency Ranking