公开(公告)号：US11665640B2

公开(公告)日：2023-05-30

申请号：US17177985

申请日：2021-02-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shiro Kamohara ,  Akira Tanabe ,  Kazuya Uejima ,  Jun Uehara ,  Kazuya Okuyama

IPC: H04W52/02 ,  H04W84/18 ,  G16Y30/00 ,  G16Y40/35

CPC classification number: H04W52/0216 ,  G16Y30/00 ,  G16Y40/35 ,  H04W52/0248 ,  H04W52/0274 ,  H04W84/18

Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.

公开(公告)号：US11604484B2

公开(公告)日：2023-03-14

申请号：US17068476

申请日：2020-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akira Tanabe ,  Kazuya Uejima

IPC: H03K17/687 ,  G05F1/44 ,  G01R31/40 ,  H01L27/092 ,  G04C10/02 ,  H03K17/00

Abstract: An electronic system device comprises a power generation device generating a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitor circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage and supplies charges based on the substrate bias voltage to the capacitor while the switch is ON-state. While the switch is OFF-state, the capacitor stores the accumulated charges based on the substrate bias voltage. While the switch is ON-state, the substrate bias generation circuit adds based on the substrate bias voltage to charge that was held, and states the back bias voltage. The substrate bias generation circuit supplies the back bias voltage to memory circuit.

公开(公告)号：US09923045B2

公开(公告)日：2018-03-20

申请号：US13681013

申请日：2012-11-19

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro Hijioka ,  Akira Tanabe ,  Yoshihiro Hayashi

IPC: H01F5/00 ,  H01F27/28 ,  H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H01F27/34

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/002 ,  H01F2017/004 ,  H01F2017/0086 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

公开(公告)号：US10854609B2

公开(公告)日：2020-12-01

申请号：US16005825

申请日：2018-06-12

Applicant: Renesas Electronics Corporation

Inventor： Akira Tanabe

IPC: H01L27/092 ,  H01L21/8234 ,  H03K17/06 ,  H01L21/8238

Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.

公开(公告)号：US10192951B2

公开(公告)日：2019-01-29

申请号：US15888594

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro Hijioka ,  Akira Tanabe ,  Yoshihiro Hayashi

IPC: H01F17/00 ,  H01L49/02 ,  H01F41/04 ,  H01F27/34

Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

公开(公告)号：US08841771B2

公开(公告)日：2014-09-23

申请号：US14075513

申请日：2013-11-08

Applicant: Renesas Electronics Corporation

Inventor： Masayuki Furumiya ,  Yasutaka Nakashiba ,  Akira Tanabe

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H01L23/481 ,  H01L21/823871 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/5286 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Abstract translation: 具有晶体管区域的半导体器件具有形成在位于信号线下方并位于晶体管区域之上的多层互连结构内的第一导体图案。 第一导体图案耦合到地或电源并与晶体管区重叠。 信号线与第一导体图案重叠。

公开(公告)号：US08604617B2

公开(公告)日：2013-12-10

申请号：US13708207

申请日：2012-12-07

Applicant: Renesas Electronics Corporation

Inventor： Masayuki Furumiya ,  Yasutaka Nakahsiba ,  Akira Tanabe

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/823871 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/5286 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

公开(公告)号：US11695010B2

公开(公告)日：2023-07-04

申请号：US17079741

申请日：2020-10-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akira Tanabe

IPC: H01L27/092 ,  H01L21/8234 ,  H03K17/06 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/823493 ,  H03K17/063 ,  H01L21/823892 ,  H03K2017/066 ,  H03K2217/0018 ,  H03K2217/0036

Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.

公开(公告)号：US10447257B2

公开(公告)日：2019-10-15

申请号：US16414846

申请日：2019-05-17

Applicant: Renesas Electronics Corporation

Inventor： Akira Tanabe

IPC: H03K3/01 ,  H03K17/30 ,  H03K17/041 ,  H03K17/10 ,  H03K17/0412

Abstract: Related-art back bias generation circuits cause a problem where a long time is required for transition between an operating state and a standby state because driving power is lowered to reduce the power consumption in the standby state. A back bias generation circuit outputs a predetermined voltage. The predetermined voltage is the back bias voltage of a substrate in a standby mode. A bias control circuit stores an electrical charge while a circuit block is in an operating mode, supplies the stored electrical charge to the substrate of a MOSFET included in the circuit block when the circuit block transitions from the operating mode to the standby mode, and subsequently supplies the output of the back bias generation circuit to the substrate of the MOSFET.

公开(公告)号：US10340905B2

公开(公告)日：2019-07-02

申请号：US15663728

申请日：2017-07-29

Applicant: Renesas Electronics Corporation

Inventor： Akira Tanabe

IPC: H03K17/04 ,  H03K17/041 ,  H03K17/10 ,  H03K17/0412

Abstract: Related-art back bias generation circuits cause a problem where a long time is required for transition between an operating state and a standby state because driving power is lowered to reduce the power consumption in the standby state. A back bias generation circuit outputs a predetermined voltage. The predetermined voltage is the back bias voltage of a substrate in a standby mode. A bias control circuit stores an electrical charge while a circuit block is in an operating mode, supplies the stored electrical charge to the substrate of a MOSFET included in the circuit block when the circuit block transitions from the operating mode to the standby mode, and subsequently supplies the output of the back bias generation circuit to the substrate of the MOSFET.