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公开(公告)号：US11665640B2
公开(公告)日：2023-05-30
申请号：US17177985
申请日：2021-02-17
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shiro Kamohara , Akira Tanabe , Kazuya Uejima , Jun Uehara , Kazuya Okuyama
CPC classification number: H04W52/0216 , G16Y30/00 , G16Y40/35 , H04W52/0248 , H04W52/0274 , H04W84/18
Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.
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公开(公告)号：US11604484B2
公开(公告)日：2023-03-14
申请号：US17068476
申请日：2020-10-12
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Akira Tanabe , Kazuya Uejima
IPC: H03K17/687 , G05F1/44 , G01R31/40 , H01L27/092 , G04C10/02 , H03K17/00
Abstract: An electronic system device comprises a power generation device generating a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitor circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage and supplies charges based on the substrate bias voltage to the capacitor while the switch is ON-state. While the switch is OFF-state, the capacitor stores the accumulated charges based on the substrate bias voltage. While the switch is ON-state, the substrate bias generation circuit adds based on the substrate bias voltage to charge that was held, and states the back bias voltage. The substrate bias generation circuit supplies the back bias voltage to memory circuit.
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公开(公告)号：US09892788B2
公开(公告)日：2018-02-13
申请号：US15224524
申请日：2016-07-30
Applicant: Renesas Electronics Corporation
Inventor： Kazuya Uejima
CPC classification number: G11C14/009 , G11C7/1006 , G11C7/20 , G11C7/24 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C14/0045
Abstract: It is required to store data to be stored for a holding period required for this data and then erase the data while suppressing power consumption. A memory device 10 to solve such a problem has the following configuration. The memory device 10 includes an ReRAM (resistance random access memory) 100 and a storage controller 101. The storage controller 101 performs control to store, in a storing condition according to a holding period required for data to be stored, the data in the ReRAM 100.
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Patent Agency Ranking
公开(公告)号：US11742356B2
公开(公告)日：2023-08-29
申请号：US17687141
申请日：2022-03-04
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuya Uejima , Kazuhiro Koudate
IPC: H01L27/12 , H03K3/356 , H03K19/00 , H03K3/012 , H03K19/0185
CPC classification number: H01L27/1207 , H03K3/012 , H03K3/35613 , H03K19/0013 , H03K19/018528
Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
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公开(公告)号：US11296118B2
公开(公告)日：2022-04-05
申请号：US17131455
申请日：2020-12-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuya Uejima , Kazuhiro Koudate
IPC: H01L27/12 , H03K3/356 , H03K3/012 , H03K19/00 , H03K19/0185
Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
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公开(公告)号：US11456665B2
公开(公告)日：2022-09-27
申请号：US16827198
申请日：2020-03-23
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuya Hashimoto , Kazuya Uejima
Abstract: An electronic system device includes a semiconductor device and a power generating device for generating a power supply voltage. The semiconductor device includes a control circuit coupled with the power generating device via a power supply node, and a substrate-biased control circuit coupled with the control circuit. The electronic system device includes a DC-DC converter, and a switch arranged between the power supply nodes and the DC-DC converter. The control circuit sets the switch to an ON state after receiving the power supply voltage. The DC-DC converter receives the power supply voltage after the switch is controlled to the ON state. The substrate bias control circuit supplies a substrate bias voltage to the control circuit before the DC-DC converter receives the power supply voltage.
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公开(公告)号：US20170290553A1
公开(公告)日：2017-10-12
申请号：US15468063
申请日：2017-03-23
Applicant: Renesas Electronics Corporation
Inventor： Masaharu Matsudaira , Takashi Hase , Akira Tanabe , Kazuya Uejima
CPC classification number: A61B5/7285 , A61B5/0002 , A61B5/002 , A61B5/01 , A61B5/021 , A61B5/1118 , A61B5/742 , A61B2560/0209 , A61B2560/0242 , A61B2560/0252 , A61B2560/0431 , A61B2560/0475 , A61B2562/029
Abstract: In order to appropriately set a condition for measurement of a sensor for measuring an object to be measured in accordance with a change of an external index that can affect the object to be measured, a sensor system includes first and second sensors, a determination unit for outputting a detection signal when a measurement result of the first sensor satisfies a predetermined condition, a measurement condition storage unit for storing a condition for measurement of the second sensor, and a control unit for performing measurement by the second sensor separately from measurement in accordance with the condition for measurement, when having received the detection signal, and for updating the condition for measurement of the second sensor stored in the measurement condition storage unit based on a result of the performed measurement.
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公开(公告)号：US09577095B2
公开(公告)日：2017-02-21
申请号：US14700461
申请日：2015-04-30
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuya Uejima , Hidetatsu Nakamura , Akihito Sakakidani , Eiichirou Watanabe
CPC classification number: H01L29/7843 , H01L21/76232 , H01L21/823807 , H01L21/823864 , H01L29/0653 , H01L29/0847 , H01L29/41758 , H01L29/45 , H01L29/6653 , H01L29/66636
Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.
Abstract translation: 半导体器件包括MISFET。 半导体器件还包括氮化硅膜12和布置在氮化硅膜12上的氮化硅膜10.氮化硅膜12覆盖MISFET的源极/漏极8的上部的至少一部分，并且具有 膜厚度比栅电极4的高度薄。源极/漏极8在其与氮化硅膜10的边界上包括硅化镍9。氮化硅膜10是应力膜。 氮化硅膜12与源极/漏极8的表面之间以及氮化硅膜12和氮化硅膜10之间的紧密附着性比使用氮化硅膜10 使其牢固地粘附到源/漏8。
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