公开(公告)号：US20180261530A1

公开(公告)日：2018-09-13

申请号：US15908597

申请日：2018-02-28

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki SEKIKAWA ,  Shigeo TOKUMITSU ,  Asuka KOMURO

IPC: H01L23/48 ,  H01L29/06 ,  H01L23/522 ,  H01L21/762 ,  H01L21/768

Abstract: A substrate contact plug which is connected to a wiring and a semiconductor substrate and does not form a circuit is formed in a seal ring region in a peripheral portion of a semiconductor chip region. The substrate contact plug is buried in a trench which is deeper than an element isolation trench.

公开(公告)号：US20170365553A1

公开(公告)日：2017-12-21

申请号：US15696395

申请日：2017-09-06

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Takahiro MORI ,  Tetsuya NITTA

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

公开(公告)号：US20180350656A1

公开(公告)日：2018-12-06

申请号：US16049938

申请日：2018-07-31

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA ,  Shigeo TOKUMITSU

IPC: H01L21/764 ,  H01L21/762 ,  H01L27/11526

CPC classification number: H01L21/764 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.

公开(公告)号：US20170288013A1

公开(公告)日：2017-10-05

申请号：US15468324

申请日：2017-03-24

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU

IPC: H01L29/04 ,  H01L23/528 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/04 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/1095

Abstract: A semiconductor device includes a high voltage transistor formation region defined by an element isolation insulating film, a transistor formation region defined by an element isolation insulating film, and a substrate contact portion. A crystal defect region is formed at a portion of a semiconductor substrate that is positioned immediately below each of the substrate contact portion and element isolation insulating films.

公开(公告)号：US20170250107A1

公开(公告)日：2017-08-31

申请号：US15594872

申请日：2017-05-15

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

Abstract: An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

公开(公告)号：US20150115410A1

公开(公告)日：2015-04-30

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Takahiro MORI ,  Tetsuya NITTA

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

Abstract translation: 多个第一布线层布置在基板的主表面上，第一绝缘膜布置在多个第一布线层的上表面上，第二绝缘膜布置在第一绝缘膜的上表面上，并且 多个第二布线层布置在第二绝缘膜上。 金属电阻元件层布置在多个第二布线层中的至少一个第二布线层正下方。 多个导电层在垂直于主表面的Z方向上从多个第二布线层分别延伸到金属电阻元件层。 金属电阻元件层包括金属布线层。 多个导电层中的至少一个导电层的侧面的至少一部分连接到金属布线层。

公开(公告)号：US20170287912A1

公开(公告)日：2017-10-05

申请号：US15463681

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Hiroki FUJII

IPC: H01L27/092 ,  H01L29/10 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L23/528 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/1095

Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.

公开(公告)号：US20170047338A1

公开(公告)日：2017-02-16

申请号：US15180484

申请日：2016-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA ,  Shigeo TOKUMITSU

IPC: H01L27/115 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8249

CPC classification number: H01L21/764 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：形成多个栅电极，在多个栅电极上形成第一绝缘膜，使得第一绝缘膜嵌入在多个栅电极之间的空间中，形成第二绝缘膜 在所述第一绝缘膜上形成绝缘膜，在所述第二绝缘膜上形成第三绝缘膜，在所述第三绝缘膜上形成感光图案，使用所述感光图案作为掩模进行蚀刻，以形成延伸穿过所述第一至第三绝缘膜的沟槽 并且到达半导体衬底，去除光敏图案，使用暴露的第三绝缘膜作为掩模进行蚀刻，以延伸半导体衬底中的沟槽，去除第三和第二绝缘膜，并在沟槽中形成第四绝缘膜 第一绝缘膜。

公开(公告)号：US20150349055A1

公开(公告)日：2015-12-03

申请号：US14704355

申请日：2015-05-05

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU

IPC: H01L29/06 ,  H01L29/861 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L21/76229 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

Abstract: An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

Abstract translation: 在基板中形成元件隔离沟槽，并且在平面图中沿多边形的每一侧形成。 第一沟槽形成在衬底中，并且沿与沟槽的任何一侧不同的方向延伸。 第一导电型区域形成在基板的第一沟槽的端部的侧面上。 因此，当在衬底中沿深度方向延伸的杂质区域通过在衬底中形成沟槽并且将杂质对角地注入到沟槽中而形成时，可以防止杂质被注入到诸如 用于元件隔离的凹槽等等，杂质注入其侧面是不期望的。

公开(公告)号：US20150295045A1

公开(公告)日：2015-10-15

申请号：US14746831

申请日：2015-06-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shigeo TOKUMITSU ,  Akio UENISHI

IPC: H01L29/10 ,  H01L29/36

CPC classification number: H01L29/1045 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.

Abstract translation: 高压晶体管包括第一杂质层，形成在第一杂质层内的第二杂质层，以将第二杂质层置于它们之间，形成在第一杂质层内部的一对第三杂质层和第四杂质层， 第五杂质层从第一杂质层的最上表面到第一杂质层的内部沿着主表面沿着第二杂质层的方向突出，并且形成在第一杂质层的最上表面上方的导电层 第二杂质层。 第四杂质层中的杂质浓度高于第三和第五杂质层中的杂质浓度，第五杂质层中的杂质浓度高于第三杂质中的杂质浓度 层。