公开(公告)号：US20180076117A1

公开(公告)日：2018-03-15

申请号：US15816812

申请日：2017-11-17

Applicant: Renesas Electronics Corporation

Inventor： Shoji HASHIZUME

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/49582 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49805 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83862 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.

公开(公告)号：US20180096961A1

公开(公告)日：2018-04-05

申请号：US15710619

申请日：2017-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shoji HASHIZUME ,  Yasushi TAKAHASHI

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L24/49 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/83862 ,  H01L2224/85205 ,  H01L2224/85385 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner portion of the lead, the semiconductor chip, and the wire are sealed by a sealing body (a resin sealing body). The wire is bonded to an upper surface of a wire bonding portion of the inner portion of the lead. A metal film is formed on a lower surface of the inner portion of the lead, which is on an opposite side to the upper surface. No metal film is formed on the upper surface of the wire bonding portion.

公开(公告)号：US20180277397A1

公开(公告)日：2018-09-27

申请号：US15900416

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Shoji HASHIZUME ,  Keita TAKADA

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/544 ,  B29C45/14 ,  B29C45/00

CPC classification number: H01L21/565 ,  B29C45/0025 ,  B29C45/0046 ,  B29C45/14336 ,  B29C45/14655 ,  B29C2045/0027 ,  B29L2031/34 ,  H01L21/4825 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H02P27/06 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00

Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.

公开(公告)号：US20170179011A1

公开(公告)日：2017-06-22

申请号：US15331902

申请日：2016-10-23

Applicant: Renesas Electronics Corporation

Inventor： Shoji HASHIZUME

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49582 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49805 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83862 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed.

公开(公告)号：US20190122900A1

公开(公告)日：2019-04-25

申请号：US16048403

申请日：2018-07-30

Applicant: Renesas Electronics Corporation

Inventor： Shoji HASHIZUME ,  Shinichi NISHIMURA

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/00

Abstract: The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.

公开(公告)号：US20190318939A1

公开(公告)日：2019-10-17

申请号：US16453719

申请日：2019-06-26

Applicant: Renesas Electronics Corporation

Inventor： Shoji HASHIZUME ,  Keita Takada

IPC: H01L21/56 ,  H01L23/495 ,  B29C45/14 ,  H01L23/31 ,  H01L21/48 ,  B29C45/00 ,  H01L23/544

Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.

公开(公告)号：US20190311974A1

公开(公告)日：2019-10-10

申请号：US16291872

申请日：2019-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shoji HASHIZUME ,  Yasushi TAKAHASHI

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 μm≤Ra≤3.0 μm holds.