公开(公告)号：US09984884B2

公开(公告)日：2018-05-29

申请号：US15385507

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/04 ,  H01L29/778 ,  H01L21/28 ,  H01L21/02 ,  H01L21/308 ,  H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

公开(公告)号：US20140110760A1

公开(公告)日：2014-04-24

申请号：US14060601

申请日：2013-10-22

Applicant: Renesas Electronics Corporation

Inventor： Ryohei Nega ,  Yoshinao Miura

IPC: H01L29/778 ,  H01L27/088 ,  H02M1/34

CPC classification number: H02M3/158 ,  H01L21/8252 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/49861 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H02M1/34 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

Abstract translation: 提供一种半导体器件，包括：DC / DC转换器电路，其中DC / DC转换器电路包括常闭型晶体管，具有连接到输入端的第一漏电极和连接到输出端的第一源电极 端子，其形成在具有二维电子气体层的第一化合物半导体衬底中，以及具有连接到第一源电极的第二漏电极和接地的第二源电极的晶体管。

公开(公告)号：US20140097445A1

公开(公告)日：2014-04-10

申请号：US14038327

申请日：2013-09-26

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao Miura

IPC: H01L29/778

CPC classification number: H01L27/0727 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A transistor SEL is formed by using a compound semiconductor layer (channel layer CNL). The channel layer CNL is formed over a buffer layer BUF. In a first direction where a drain electrode DRE, a gate electrode GE, and a source electrode SOE of the transistor SEL are arranged, at least a portion of the buried electrode BE is situated on the side opposing the source electrode SOE with reference to the gate electrode GE. The buried electrode BE is connected to the source electrode SOE of the transistor SEL. The top end of the buried electrode BE intrudes into the buffer layer BUF.

Abstract translation: 通过使用化合物半导体层（沟道层CNL）形成晶体管SEL。 沟道层CNL形成在缓冲层BUF上。 在晶体管SEL的漏电极DRE，栅电极GE，源电极SOE的第一方向上，埋入电极BE的至少一部分位于与源电极SOE相对的一侧， 栅电极GE。 埋入电极BE连接到晶体管SEL的源极SOE。 埋入电极BE的顶端侵入缓冲层BUF。

公开(公告)号：US10290583B2

公开(公告)日：2019-05-14

申请号：US15467051

申请日：2017-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinao Miura

IPC: H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L23/528

Abstract: An object of the present invention is to shorten the switching delay time of a semiconductor device.Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.

公开(公告)号：US10135337B2

公开(公告)日：2018-11-20

申请号：US15491875

申请日：2017-04-19

Applicant: Renesas Electronics Corporation

Inventor： Ryohei Nega ,  Yoshinao Miura

IPC: H01L29/778 ,  H02M3/158 ,  H02M1/34 ,  H01L29/205 ,  H01L23/498 ,  H01L29/20 ,  H01L29/423

Abstract: Provided is a semiconductor device including a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

公开(公告)号：US10032736B2

公开(公告)日：2018-07-24

申请号：US14494409

申请日：2014-09-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinao Miura ,  Takashi Nakamura ,  Tadatoshi Danno

IPC: H01L23/538 ,  H01L23/00 ,  H01L27/088 ,  H01L27/02 ,  H01L29/778 ,  H01L27/06 ,  H01L27/085 ,  H01L23/482 ,  H01L23/495 ,  H01L29/20

Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

公开(公告)号：US10014403B2

公开(公告)日：2018-07-03

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/15 ,  H01L29/201 ,  H01L21/027 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/205 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

公开(公告)号：US20180151377A1

公开(公告)日：2018-05-31

申请号：US15882687

申请日：2018-01-29

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

公开(公告)号：US09667147B2

公开(公告)日：2017-05-30

申请号：US15065762

申请日：2016-03-09

Applicant: Renesas Electronics Corporation

Inventor： Ryohei Nega ,  Yoshinao Miura

IPC: H01L23/495 ,  H02M3/158 ,  H01L29/778 ,  H01L27/088 ,  H02M1/34 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/205 ,  H01L29/20 ,  H01L23/498

CPC classification number: H02M3/158 ,  H01L21/8252 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/49861 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H02M1/34 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

公开(公告)号：US20170103898A1

公开(公告)日：2017-04-13

申请号：US15385507

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/778 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.