公开(公告)号：US10043707B2

公开(公告)日：2018-08-07

申请号：US13850588

申请日：2013-03-26

Applicant: RF Micro Devices, Inc.

Inventor： John August Orlowski ,  David Jandzinski

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/495 ,  H01L21/48

Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.

公开(公告)号：US20150201515A1

公开(公告)日：2015-07-16

申请号：US14595615

申请日：2015-01-13

Applicant: RF Micro Devices, Inc.

Inventor： Donald Joseph Leahy ,  Jungwoo Lee ,  John August Orlowski ,  Howard Joseph Holyoak

IPC: H05K7/06 ,  H05K13/00 ,  H05K1/09

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/81444 ,  H01L2224/85444 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/181 ,  H05K1/09 ,  H05K3/244 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0338 ,  H05K2201/10674 ,  H05K2203/049 ,  H05K2203/1316 ,  Y10T29/49162 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronics module includes a non-conductive body, a first set of conductive features exposed on a surface of the non-conductive body, and a second set of conductive features exposed on the surface of the non-conductive body. The first set of conductive features is configured to connect to a wire bond component. The second set of conductive features is configured to connect to a flip chip component. A protective finish is provided over each one of the first set of conductive features and the second set of conductive features. The protective finish includes a layer of nickel less than 1 μm thick, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium.

Abstract translation: 电子模块包括非导电体，暴露在非导电体的表面上的第一组导电特征，以及暴露在非导电体的表面上的第二组导电特征。 第一组导电特征被配置成连接到引线接合部件。 第二组导电特征被配置为连接到倒装芯片部件。 在第一组导电特征和第二组导电特征中的每一个上提供保护整理。 保护层包括一层厚度小于1μm的镍层，镍层上的一层钯层和钯层上的一层金。

公开(公告)号：US20140144682A1

公开(公告)日：2014-05-29

申请号：US13891888

申请日：2013-05-10

Applicant: RF MICRO DEVICES, INC.

Inventor： John August Orlowski ,  Donald Joseph Leahy

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H05K3/00 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2924/181 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/073 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047

Abstract: An electronic substrate includes one or more conductive features. In order to preserve the performance and conductivity of the one or more conductive features, the exposed portions of the conductive features are deposited with a protective layer comprising a layer of silver, followed by a layer of gold. By covering the exposed portions of the conductive features of the electronic substrate with the protective layer, oxidation and exposure of the conductive features is prevented, thereby preserving the performance and conductivity of the copper features. Further, during a soldering process, the protective layer is substantially dissolved, thereby allowing the solder to join directly with the underlying conductive features and improving the performance of the electronic substrate.

Abstract translation: 电子基板包括一个或多个导电特征。 为了保持一个或多个导电特征的性能和导电性，导电特征的暴露部分被沉积有包含一层银的保护层，随后是一层金。 通过用保护层覆盖电子基板的导电特征的暴露部分，防止导电特征的氧化和曝光，从而保持铜特征的性能和导电性。 此外，在焊接工艺期间，保护层基本上溶解，从而允许焊料直接与下面的导电特征相结合并且改善了电子衬底的性能。

公开(公告)号：US20140106564A1

公开(公告)日：2014-04-17

申请号：US13850588

申请日：2013-03-26

Applicant: RF MICRO DEVICES, INC.

Inventor： John August Orlowski ,  David Jandzinski

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  H01L21/4832 ,  H01L23/49582 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.

Abstract translation: 选择性地电镀第一可镀层以形成一个或多个再分布路径。 IC封装的连接点连接到再分配路径，并且IC封装过度模制以确保稳定性。 然后去除第一耐热层，留下暴露的一个或多个再分布路径。 再分配路径允许IC封装的一个或多个接触点移动到新位置，以便于将IC封装集成到系统中。 通过从第一可镀层向上镀覆再分配路径，实现了不需要专门制造设备的精细几何形状，用于以最小的导体厚度重新定位IC封装的接触点。 因此，以低成本形成再分布层，同时最小化层对IC器件的操作的影响。

公开(公告)号：US20140146489A1

公开(公告)日：2014-05-29

申请号：US13891809

申请日：2013-05-10

Applicant: RF Micro Devices, Inc.

Inventor： John August Orlowski ,  Donald Joseph Leahy ,  Thomas Scott Morris ,  David C. Dening ,  David Jandzinski

IPC: H05K1/02 ,  H05K3/38

CPC classification number: H05K3/3436 ,  H05K1/111 ,  H05K3/244 ,  H05K3/3452 ,  H05K2201/0338 ,  H05K2201/099 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic substrate includes a non-conductive body and one or more conductive features coupled to the non-conductive body. Each of the conductive features includes a base layer. To preserve the performance and conductivity of the one or more conductive features, each of the conductive features includes a protective layer formed over the base layer. The protective layer may include a first layer of silver formed over the base layer and a second layer of palladium formed over the first layer. By depositing the protective layer over the base layer of each of the conductive features, oxidation and exposure of the conductive features is prevented, or at least substantially reduced, since the first layer and the second layer provide a migration barrier for the metal in the base layer. However, the performance and conductivity of the conductive features are maintained due to the low resistivity of silver and palladium.

Abstract translation: 电子基板包括非导电体和耦合到非导电体的一个或多个导电特征。 每个导电特征包括基层。 为了保持一个或多个导电特征的性能和导电性，每个导电特征包括形成在基底层上的保护层。 保护层可以包括在基底层上形成的第一层银，以及形成在第一层上的第二层钯。 通过在每个导电特征的基底层上沉积保护层，防止或至少基本上减少了导电特征的氧化和曝光，因为第一层和第二层为基底中的金属提供迁移屏障 层。 然而，由于银和钯的低电阻率，导电特征的性能和导电性得以保持。