公开(公告)号：US5059243A

公开(公告)日：1991-10-22

申请号：US344878

申请日：1989-04-28

申请人： Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

发明人： Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

IPC分类号： C23C18/40

CPC分类号： C23C18/40

摘要： An electroless copper plating bath uses a series of tetradentate nitrogen ligands. The components of the bath may be substituted without extensive re-optimization of the bath. The Cu-tetra-aza ligand baths operates over a pH range between 7 and 12. Stable bath formulations employing various buffers, reducing agents and ligands have been developed. The process can be used for metal deposition at lower pH and provides the capability to use additive processing for metallization in the presence of polyimide, positive photoresist and other alkali sensitive substrates.

公开(公告)号：US5102456A

公开(公告)日：1992-04-07

申请号：US618769

申请日：1990-11-27

申请人： Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

发明人： Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

IPC分类号： C23C18/40

CPC分类号： C23C18/40 ,  Y10T428/12694 ,  Y10T428/12903 ,  Y10T428/31681

摘要： An electroless copper plating bath uses a series of tetradentate nitrogen ligands. The components of the bath may be substituted without extensive re-optimization of the bath. The Cu-tetra-aza ligand baths operates over a pH range between 7 and 12. Stable bath formulations employing various buffers, reducing agents and ligands have been developed. The process can be used for metal deposition at lower pH and provides the capability to use additive processing for metallization in the presence of polyimide, positive photoresist and other alkali sensitive substrates.

摘要翻译： 化学镀铜浴使用一系列四齿氮配体。 浴的组分可以被代替而没有大量重新优化浴。 Cu-四氮杂配体浴在7和12之间的pH范围内运行。已经开发了使用各种缓冲液，还原剂和配体的稳定浴配方。 该方法可用于较低pH下的金属沉积，并提供在聚酰亚胺，正性光致抗蚀剂和其他碱敏感基材存在下使用添加剂处理进行金属化的能力。

公开(公告)号：US20090309228A1

公开(公告)日：2009-12-17

申请号：US12539660

申请日：2009-08-12

申请人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

发明人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

IPC分类号： H01L23/532 ,  H01L21/306

CPC分类号： H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

摘要翻译： 本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。 更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

公开(公告)号：US08101518B2

公开(公告)日：2012-01-24

申请号：US12136885

申请日：2008-06-11

申请人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 在退火步骤A期间，与绝缘材料（例如SiO 2和Si 3 N 4）直接接触的金属不会转化为金属合金硅化物接触。然后进行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属 。

公开(公告)号：US08039382B2

公开(公告)日：2011-10-18

申请号：US12539660

申请日：2009-08-12

申请人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

发明人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

IPC分类号： H01L21/00

CPC分类号： H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

摘要翻译： 本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。 更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

公开(公告)号：US07618891B2

公开(公告)日：2009-11-17

申请号：US11415922

申请日：2006-05-01

申请人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

发明人： Sunfei Fang ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee T. Mo ,  Balasubramanian Pranatharthiharan ,  Jay W. Strane

IPC分类号： H01L21/00

CPC分类号： H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

摘要翻译： 本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。 更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

公开(公告)号：US07544610B2

公开(公告)日：2009-06-09

申请号：US10935497

申请日：2004-09-07

申请人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/477 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 在绝缘材料如SiO 2和Si 3 N 4中直接接触的金属在退火步骤期间不会转化为金属合金硅化物接触。 然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US20080274611A1

公开(公告)日：2008-11-06

申请号：US12136885

申请日：2008-06-11

申请人： Cyril Cabral ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触 然后执行退火步骤A选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US06992389B2

公开(公告)日：2006-01-31

申请号：US10709321

申请日：2004-04-28

申请人： Panayotis C. Andricacos ,  Tien-Jen J. Cheng ,  Emanuel I. Cooper ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Roger A. Quon ,  Erik J. Roggeman

发明人： Panayotis C. Andricacos ,  Tien-Jen J. Cheng ,  Emanuel I. Cooper ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Roger A. Quon ,  Erik J. Roggeman

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L21/2885 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/00014

摘要： A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

摘要翻译： 创建用于在互连中使用的多层屏障的方法，用于互连的阻挡，以及包括该阻挡互连中公开。 该方法包括通过使用单个电镀化学品在器件端子的凹部中产生多层屏障，以增强由于铜的扩散而导致的排除和去层压的保护，无论是通过自扩散还是电迁移。 所述屏障至少包括富镍材料制成的第一层和富铜材料制成的第二层。 该屏障允许使用用于高级互补金属氧化物半导体（CMOS）的设计更高的电流密度的，并延伸当前的CMOS的可靠性设计不管焊料选择。 此外，这种技术很容易适应制造电镀互连，如C4S的当前方法。

公开(公告)号：US08592266B2

公开(公告)日：2013-11-26

申请号：US12912963

申请日：2010-10-27

申请人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

发明人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.