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    RELIABLE NANOFET BIOSENSOR PROCESS WITH HIGH-K DIELECTRIC
    1.
    发明申请
    RELIABLE NANOFET BIOSENSOR PROCESS WITH HIGH-K DIELECTRIC 审中-公开
    具有高K电介质的可靠的纳米ZnO生物传感器工艺

    公开(公告)号：US20140054651A1

    公开(公告)日：2014-02-27

    申请号：US13992217

    申请日：2011-11-18

    申请人： Rashid Bashir ,  Bobby Reddy ,  Brian Ross Dorvel

    发明人： Rashid Bashir ,  Bobby Reddy ,  Brian Ross Dorvel

    IPC分类号： G01N27/414

    CPC分类号： G01N27/4145

    摘要： Provided are semiconductor field effect sensors including a high-k thin film gate dielectric. The semiconductor field effect sensors described herein exhibit high detection sensitivity and enhanced reliability when placed in contact with liquids. Also disclosed are semiconductor field effect sensors having optimized fluid gate electrode voltages and/or back gate electrode voltages for improved detection sensitivity.

    摘要翻译： 提供了包括高k薄膜栅极电介质的半导体场效应传感器。 当与液体接触时，本文所述的半导体场效应传感器表现出高检测灵敏度和增强的可靠性。 还公开了具有优化的流体栅电极电压和/或背栅电极电压的半导体场效应传感器，以提高检测灵敏度。

    Elimination of walkout in high voltage trench isolated devices
    6.
    发明授权
    Elimination of walkout in high voltage trench isolated devices 失效

    公开(公告)号：US06362064B1

    公开(公告)日：2002-03-26

    申请号：US09063074

    申请日：1998-04-21

    申请人： Joel M. McGregor ,  Rashid Bashir ,  Wipawan Yindeepol

    发明人： Joel M. McGregor ,  Rashid Bashir ,  Wipawan Yindeepol

    IPC分类号： H01L21331

    摘要： Walkout in high voltage trench isolated semiconductor devices is inhibited by applying a voltage bias signal directly to epitaxial silicon surrounding the device. Voltage applied to the surrounding epitaxial silicon elevates the initial breakdown voltage of the device and eliminates walkout. This is because voltage applied to the surrounding epitaxial silicon reduces the strength of the electric field between the silicon of the device and the surrounding silicon. Specifically, application of a positive voltage bias signal to surrounding epitaxial silicon equal to or more positive than the most positive potential occurring at the collector during normal operation of the device ensures that no walkout will occur.

    Method for controlling an N-type dopant concentration depth profile in bipolar transistor epitaxial layers
    7.
    发明授权
    Method for controlling an N-type dopant concentration depth profile in bipolar transistor epitaxial layers 有权
    用于控制双极晶体管外延层中的N型掺杂浓度深度分布的方法

    公开(公告)号：US06346452B1

    公开(公告)日：2002-02-12

    申请号：US09303957

    申请日：1999-05-03

    申请人： Abul Ehsanul Kabir ,  Rashid Bashir

    发明人： Abul Ehsanul Kabir ,  Rashid Bashir

    IPC分类号： H01L218222

    CPC分类号： H01L29/66242 ,  H01L29/36 ,  H01L29/66272

    摘要： Process for the formation of epitaxial layers with controlled n-type dopant concentration depth profiles for use in NPN bipolar transistors. The process includes first providing a semiconductor substrate (e.g. a [100]-oriented silicon wafer substrate) with an n-type collector precursor region formed on its surface, followed by forming an n-type (e.g. phosphorous or arsenic) in-situ doped epitaxial layer of a thickness t1 on the n-type collector precursor region. Next, an undoped epitaxial layer of a thickness t2 is formed on the n-type in-situ doped epitaxial layer. A p-type (e.g. boron) in-situ doped epitaxial base layer is subsequently formed on the undoped epitaxial layer. The process can also include the sequential formation of an undoped Si1−xGex epitaxial layer and a p-type in-situ doped Si1−xGex epitaxial layer between the undoped epitaxial layer and the p-type in-situ doped epitaxial base layer. Accumulation of the n-type dopant concentration in p-type epitaxial layers (such as the p-type in-situ doped epitaxial base layer or the p-type in-situ doped Si1−xGex epitaxial layer) that are formed subsequent to a non-p-type epitaxial layer (such as the undoped epitaxial layer or undoped Si1−xGex epitaxial layer, respectively) is controlled by manipulating the thickness ratio of t2 to t1, while keeping the thickness of N-layer fixed at t (i.e. t1+t2).

    摘要翻译： 用于形成具有用于NPN双极晶体管的受控n型掺杂浓度深度分布的外延层的工艺。 该方法包括首先在其表面上形成n型集电极前体区，然后形成n型（例如磷或砷）原位掺杂的半导体衬底（例如[100]取向硅晶片衬底） 在n型集电极前体区域上具有厚度t1的外延层。 接下来，在n型原位掺杂外延层上形成厚度为t2的未掺杂的外延层。 随后在未掺杂的外延层上形成p型（例如硼）原位掺杂的外延基底层。 该工艺还可以包括在未掺杂的外延层和p型原位掺杂的外延基底层之间顺序地形成未掺杂的Si1-xGex外延层和p型原位掺杂的Si1-xGex外延层。 p型外延层（例如p型原位掺杂外延基底层或p型原位掺杂的Si1-xGex外延层）中的n型掺杂剂浓度的积累是在非 - p型外延层（例如未掺杂的外延层或未掺杂的Si1-xGex外延层）分别通过操纵t2至t1的厚度比来控制，同时保持N层的厚度固定在t（即t1 + t2）。

    Complementary Si/SiGe heterojunction bipolar technology
    8.
    发明授权
    Complementary Si/SiGe heterojunction bipolar technology 失效
    互补Si / SiGe异质结双极技术

    公开(公告)号：US5930635A

    公开(公告)日：1999-07-27

    申请号：US850610

    申请日：1997-05-02

    申请人： Rashid Bashir ,  Francois Hebert

    发明人： Rashid Bashir ,  Francois Hebert

    IPC分类号： H01L21/8228 ,  H01L21/331

    CPC分类号： H01L21/8228

    摘要： A method of manufacturing truly complementary bipolar transistors on a common substrate. The method results in the fabrication of vertical NPN and PNP transistors which have an identical structure and mode of operation, with both devices operating in the downward direction. The inventive method permits independent control of the characteristics of the two devices, producing a closely matched performance for both devices.

    摘要翻译： 在公共衬底上制造真正互补的双极晶体管的方法。 该方法导致制造具有相同结构和操作模式的垂直NPN和PNP晶体管，两个器件在向下的方向上工作。 本发明的方法允许独立控制两个装置的特性，从而产生两个装置的紧密匹配的性能。

    Semiconductor device trench isolation structure with polysilicon bias voltage contact
    9.
    发明授权
    Semiconductor device trench isolation structure with polysilicon bias voltage contact 失效
    半导体器件沟槽隔离结构与多晶硅偏压接触

    公开(公告)号：US5914523A

    公开(公告)日：1999-06-22

    申请号：US24329

    申请日：1998-02-17

    申请人： Rashid Bashir ,  Wipawan Yindeepol

    发明人： Rashid Bashir ,  Wipawan Yindeepol

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/765 ,  H01L23/58

    CPC分类号： H01L21/76264 ,  H01L21/763 ,  H01L21/765 ,  H01L21/76275 ,  H01L21/76286

    摘要： A semiconductor device, polysilicon-contacted trench isolation- structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate. After forming layers of trench lining oxide, trench lining silicon nitride and trench fill poly 1 in the isolation trench, the trench lining silicon nitride is etched back to expose lateral surfaces of the trench fill poly 1. A poly 2 layer is then deposited and makes contact with the exposed lateral surfaces of the trench fill poly 1.

    摘要翻译： 提供改善的电隔离稳定性的半导体器件，多晶硅接触沟槽隔离结构，操作多晶硅接触沟槽隔离半导体器件的方法，以及用于制造多晶硅接触沟槽隔离结构的工艺。 沟槽隔离结构包括形成在半导体衬底中的隔离沟槽。 隔离沟槽具有一层沟槽衬垫氧化物，一层沟槽衬里氮化硅和沟槽填充多晶硅（poly 1）层。 在沟槽衬套氮化硅之上延伸的聚1的暴露的侧表面与另一层多晶硅（聚2）接触。 操作方法包括通过多晶硅2向沟槽填充多晶硅层1施加偏置电压。制造方法包括蚀刻延伸穿过场氧化物层并进入半导体衬底的隔离沟槽。 在形成沟槽衬垫氧化物层之后，沟槽衬里氮化硅和沟槽填充聚合物1在隔离沟槽中，沟槽衬里氮化硅被回蚀刻以暴露沟槽填充聚合物1的侧表面。然后沉积聚二层 与沟槽填充聚1的暴露的侧表面接触。

    Tungsten silicide/ tungsten polycide anisotropic dry etch process
    10.
    发明授权
    Tungsten silicide/ tungsten polycide anisotropic dry etch process 失效
    硅化钨/聚硅氧烷多向干蚀刻工艺

    公开(公告)号：US5856239A

    公开(公告)日：1999-01-05

    申请号：US850573

    申请日：1997-05-02

    申请人： Rashid Bashir ,  Abul Ehsanul Kabir ,  Francois Hebert

    发明人： Rashid Bashir ,  Abul Ehsanul Kabir ,  Francois Hebert

    IPC分类号： H01L21/3213 ,  H01L21/00

    CPC分类号： H01L21/32137

    摘要： A process for anisotropically etching a tungsten silicide or tungsten polycide structure. If the silicide/polycide film has an overlying oxide layer, the insulating layer is removed by a gas mixture composed of CHF.sub.3 and C.sub.2 F.sub.6. The WSi.sub.x silicide layer is then etched in a reactive ion etch using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6, with sufficient O.sub.2 added to control polymer formation and prevent undercutting of the silicide. The polysilicon layer is then etched using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6. The result is a highly anisotropic etch process which preserves the critical dimension of the etched structures. The etch parameters may be varied to produce a tapered sidewall profile for use in the formation of butted contacts without the need for a contact mask.

    摘要翻译： 用于各向异性蚀刻硅化钨或聚钨酸钨结构的方法。 如果硅化物/多硅化物膜具有上覆氧化物层，则通过由CHF 3和C 2 F 6组成的气体混合物除去绝缘层。 然后使用由Cl 2和C 2 F 6形成的气体混合物在反应离子蚀刻中对WSix硅化物层进行蚀刻，加入足够的O 2以控制聚合物形成并防止硅化物的底切。 然后使用由Cl 2和C 2 F 6形成的气体混合物来蚀刻多晶硅层。 结果是高度各向异性的蚀刻工艺，其保留蚀刻结构的临界尺寸。 可以改变蚀刻参数以产生用于形成对接触点的锥形侧壁轮廓，而不需要接触掩模。