公开(公告)号：US20080078985A1

公开(公告)日：2008-04-03

申请号：US11864426

申请日：2007-09-28

申请人： Rene Meyer ,  Paul McIntyre

发明人： Rene Meyer ,  Paul McIntyre

IPC分类号： H01L47/00

CPC分类号： G11C13/02 ,  G11C2213/11 ,  H01L45/08 ,  H01L45/12 ,  H01L45/142 ,  H01L45/146 ,  H01L45/147

摘要： Non-volatile resistance change memories, systems, arrangements and associated methods are implemented in a variety of embodiments. According to one embodiment, a memory cell having two sections with outwardly-facing portions, the outwardly-facing portions electrically coupled to electrodes is implemented. The memory cell has an ionic barrier between the two sections. The two sections and the ionic barrier facilitate movement of ions from one of the two sections to the other of the two sections in response to a first voltage differential across the outwardly-facing portions. The two sections and the ionic barrier diminish movement of ions from the one of the two sections to the other of the two sections in response to another voltage differential across the outwardly-facing portions.

摘要翻译： 在各种实施例中实现非易失性电阻变化存储器，系统，布置和相关联的方法。 根据一个实施例，实现了具有两个部分的存储单元，其具有朝外的部分，电耦合到电极的朝外的部分被实现。 记忆单元在两个部分之间具有离子屏障。 两个部分和离子屏障促使离子从两个部分中的一个移动到两个部分中的另一个部分，以响应跨越面向外部分的第一电压差。 两个部分和离子屏障响应于穿过面向外部分的另一个电压差，使离子从两个部分中的一个部分移动到两个部分中的另一个部分。

公开(公告)号：US20130043452A1

公开(公告)日：2013-02-21

申请号：US13210342

申请日：2011-08-15

申请人： Rene Meyer ,  Jian Wu ,  Julie Casperson Brewer

发明人： Rene Meyer ,  Jian Wu ,  Julie Casperson Brewer

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/2463 ,  H01L27/101 ,  H01L45/08 ,  H01L45/147 ,  H01L45/1616

摘要： Structures and methods to enhance cycling endurance of BEOL memory elements are disclosed. In some embodiments, a memory element can include a support layer having a smooth and planar upper surface as deposited or as created by additional processing. A first electrode is formed the smooth and planar upper surface. The support layer can be configured to influence the formation of the first electrode to determine a substantially smooth surface of the first electrode. The memory element is formed over the first electrode having the substantially smooth surface, the memory element including one or more layers of an insulating metal oxide (IMO) operative to exchange ions to store a plurality of resistive states. The substantially smooth surface of the first electrode provides for uniform current densities through unit cross-sectional areas of the IMO. The memory element can include one or more layers of a conductive metal oxide (CMO).

摘要翻译： 公开了增强BEOL存储元件的循环耐久性的结构和方法。 在一些实施例中，存储元件可以包括具有沉积的平滑和平坦的上表面的支撑层，或者通过附加处理产生的支撑层。 第一电极形成平滑且平坦的上表面。 支撑层可以被配置为影响第一电极的形成，以确定第一电极的基本平滑的表面。 存储元件形成在具有基本平滑表面的第一电极之上，存储元件包括一层或多层绝缘金属氧化物（IMO），其可操作以交换离子以存储多个电阻状态。 第一电极的基本平滑的表面通过IMO的单元横截面区域提供均匀的电流密度。 存储元件可以包括一层或多层导电金属氧化物（CMO）。

公开(公告)号：US08268667B2

公开(公告)日：2012-09-18

申请号：US13215895

申请日：2011-08-23

申请人： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

发明人： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

IPC分类号： H01L21/00

CPC分类号： F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

摘要翻译： 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US08031510B2

公开(公告)日：2011-10-04

申请号：US12803810

申请日：2010-07-06

申请人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

发明人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

公开(公告)号：US20110149636A1

公开(公告)日：2011-06-23

申请号：US12803810

申请日：2010-07-06

申请人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lamberston ,  Julie Casperson Brewer

发明人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lamberston ,  Julie Casperson Brewer

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

公开(公告)号：US20110149634A1

公开(公告)日：2011-06-23

申请号：US12653838

申请日：2009-12-18

申请人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

发明人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

IPC分类号： G11C11/00 ,  H01L45/00 ,  H01L29/12

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

公开(公告)号：US08565006B2

公开(公告)日：2013-10-22

申请号：US13719106

申请日：2012-12-18

申请人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

发明人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

IPC分类号： G11C13/00

CPC分类号： H01L45/085 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

摘要： A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

摘要翻译： 公开了包括与导电金属氧化物（CMO）接触的电解绝缘体的存储元件的存储单元。 CMO包括晶体结构并且可以包含烧绿石氧化物，导电二元氧化物，多个B位钙钛矿和Ruddlesden-Popper结构。 CMO包括可以响应于施加在电解绝缘体和CMO上施加的写入电压产生的适当幅度和方向的电场，可以将其输送到电解绝缘体/从电解绝缘体传输的移动离子。 存储器单元可以包括与存储元件电串联的非欧姆器件（NOD）。 存储器单元可以位于单层存储器中的两端交叉点存储器阵列中的导电阵列线的交叉点或多个垂直堆叠的存储器层之间，该衬底层在衬底上制造，该衬底包括用于数据的有源电路 对数组层进行操作。

公开(公告)号：US08264864B2

公开(公告)日：2012-09-11

申请号：US12653835

申请日：2009-12-18

申请人： Rene Meyer

发明人： Rene Meyer

IPC分类号： G11C11/00

CPC分类号： H01L45/12 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

摘要： A memory device with band gap control is described. A memory cell can include a conductive oxide layer in contact with and electrically in series with an electronically insulating layer. A thickness of the electronically insulating layer is configured to increase from an initial thickness to a target thickness. The increased thickness of the electronically insulating layer can improve resistive memory effect, increase a magnitude of a read current during read operations, and lower barrier height with a concomitant reduction in band gap of the electronically insulating layer. The memory cell can include a memory element that comprises the conductive oxide layer and the electronically insulating layer and can optionally include a non-ohmic device (NOD). The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines across which voltages for data operations are applied. The memory cell and array can be fabricated BEOL.

摘要翻译： 描述了具有带隙控制的存储器件。 存储单元可以包括与电绝缘层接触并与电绝缘层串联的导电氧化物层。 电绝缘层的厚度被配置为从初始厚度增加到目标厚度。 电绝缘层的增加的厚度可以改善电阻记忆效应，增加读取操作期间的读取电流的大小，并且随着电子绝缘层的带隙的伴随的减少而降低势垒高度。 存储单元可以包括存储元件，其包括导电氧化物层和电绝缘层，并且可以可选地包括非欧姆器件（NOD）。 存储器单元可以被定位在一对导电阵列线之间的两端交叉点阵列中，用于数据操作的电压施加在该导体阵列线之间。 存储单元和阵列可以制作BEOL。

公开(公告)号：US08058643B2

公开(公告)日：2011-11-15

申请号：US11864426

申请日：2007-09-28

申请人： Rene Meyer ,  Paul C. McIntyre

发明人： Rene Meyer ,  Paul C. McIntyre

IPC分类号： H01L31/0336

CPC分类号： G11C13/02 ,  G11C2213/11 ,  H01L45/08 ,  H01L45/12 ,  H01L45/142 ,  H01L45/146 ,  H01L45/147

摘要： Non-volatile resistance change memories, systems, arrangements and associated methods are implemented in a variety of embodiments. According to one embodiment, a memory cell having two sections with outwardly-facing portions, the outwardly-facing portions electrically coupled to electrodes is implemented. The memory cell has an ionic barrier between the two sections. The two sections and the ionic barrier facilitate movement of ions from one of the two sections to the other of the two sections in response to a first voltage differential across the outwardly-facing portions. The two sections and the ionic barrier diminish movement of ions from the one of the two sections to the other of the two sections in response to another voltage differential across the outwardly-facing portions.

摘要翻译： 在各种实施例中实现非易失性电阻变化存储器，系统，布置和相关联的方法。 根据一个实施例，实现了具有两个部分的存储单元，其具有朝外的部分，电耦合到电极的朝外的部分被实现。 记忆单元在两个部分之间具有离子屏障。 两个部分和离子屏障促使离子从两个部分中的一个移动到两个部分中的另一个部分，以响应跨越面向外部分的第一电压差。 两个部分和离子屏障响应于穿过面向外部分的另一个电压差，使离子从两个部分中的一个部分移动到两个部分中的另一个部分。

公开(公告)号：US07619268B2

公开(公告)日：2009-11-17

申请号：US10544924

申请日：2004-01-07

申请人： Herman Kohlstedt ,  Rene Meyer

发明人： Herman Kohlstedt ,  Rene Meyer

IPC分类号： H01L29/92

CPC分类号： G11C11/22 ,  H01L27/11502

摘要： Memory element consisting of an electrode (2), a ferroelectric layer (3) adjoining the latter, a layer (4) made from non-ferroelectric material adjoining the ferroelectric layer (3) and an electrode (5) adjoining the layer (4) made from non-ferroelectric material, wherein the ferroelectric layer is at least 10 nanometers thick, the electrical resistance, which is formed by the non-ferroelectric layer and the ferroelectric layer, depends upon the direction of polarization in the ferroelectric layer, and wherein the memory element comprises means for measuring the electrical resistance of the non-ferroelectric layer and the ferroelectric layer.

摘要翻译： 存储元件由电极（2），与之相邻的铁电体层（3）构成，由邻接铁电体层（3）的非铁电材料制成的层（4）和邻接层（4）的电极（5） 由非铁电材料制成，其中铁电层为至少10纳米厚，由非铁电层和铁电层形成的电阻取决于铁电层中的极化方向，并且其中 存储元件包括用于测量非铁电层和铁电层的电阻的装置。