公开(公告)号：US20150124539A1

公开(公告)日：2015-05-07

申请号：US14526483

申请日：2014-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaaki IIJIMA

IPC: G11C11/419

CPC classification number: G11C11/4076 ,  G11C7/1084 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4096

Abstract: The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential and from before the start timing of a preamble of the two signals. A second comparator circuit compares the level of DQS or DQSB with a reference voltage Vref and outputs a signal ODT_DET representing the result of the comparison. A gate circuit masks the signal DQSIN with a signal EW in a masking state. A control circuit identifies the start timing of the preamble based on ODT_DET, and sets the signal EW to the masking state before the start of the preamble and to an unmasking state from the start timing of the preamble.

Abstract translation: 问题是不能防止信号DQS与DQSB之间的差异的高阻抗状态被引入。通过本发明，在输入端子耦合之后，第一比较器电路输出表示DQS与DQSB之间的差值的信号DQSIN 到两个信号的前导码的开始定时之前的终端电位。 第二比较器电路将DQS或DQSB的电平与参考电压Vref进行比较，并输出表示比较结果的信号ODT_DET。 门电路在掩蔽状态下用信号EW屏蔽信号DQSIN。 控制电路基于ODT_DET来识别前导码的开始定时，并且将信号EW设置为在前导码开始之前的屏蔽状态，并从前导码的开始定时开始到非屏蔽状态。

公开(公告)号：US20140312981A1

公开(公告)日：2014-10-23

申请号：US14244800

申请日：2014-04-03

Applicant: Renesas Electronics Corporation

Inventor： Takashi NAKAMURA ,  Kosuke YAYAMA ,  Masaaki IIJIMA

IPC: H03L7/06

CPC classification number: H03L7/0991 ,  H03L1/022 ,  H03L7/00 ,  H03L7/02 ,  H03L7/06 ,  H03L7/099 ,  H03L7/16 ,  H03L7/22 ,  H03L2207/06 ,  H03L2207/50

Abstract: A frequency-locked loop circuit includes: a digital control oscillator that generates a clock; and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes: a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit and outputs the frequency control code to the digital control oscillator.

Abstract translation: 锁频环路电路包括：产生时钟的数字控制振荡器; 以及FLL控制器，其生成用于控制时钟的振荡频率的频率控制码。 FLL控制器包括：频率比较单元，其将由数字控制振荡器产生的时钟的频率与相乘的参考时钟的频率进行比较; 以及延迟码控制单元，其基于频率比较单元的比较结果生成频率控制码，使得由数字控制振荡器产生的时钟的频率与倍增的参考时钟的频率相匹配。 频率比较单元通过使用第一和第二阈值来确定时钟的频率。 延迟代码控制单元根据频率比较单元的确定产生频率控制代码，并将频率控制代码输出到数字控制振荡器。

公开(公告)号：US20170076777A1

公开(公告)日：2017-03-16

申请号：US15360404

申请日：2016-11-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaaki IIJIMA ,  Mitsuhiro DEGUCHI

IPC: G11C11/4076 ,  H03K5/159

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/028 ,  H03K5/159 ,  H03K19/0016 ,  H03K19/096

Abstract: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal (CK) and receives a data signal (DQ) and a strobe signal (DQS) from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal (DQS). The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal (DQS) in a plurality of steps in accordance with the set frequency of the clock signal (CK). The second adjustment circuit is capable of adjusting the delay amount of the strobe signal (DQS) with a higher precision than the first adjustment circuit.

Abstract translation: 设置在半导体装置中的接口电路基于时钟信号（CK）向外部存储器件提供操作时钟，并从外部存储器件接收数据信号（DQ）和选通信号（DQS）。 接口电路包括延迟接收的选通信号（DQS）的延迟电路。 延迟电路包括与第一调整电路串联连接的第一调整电路和第二调整电路。 第一调整电路能够根据时钟信号（CK）的设定频率，在多个步骤中调整选通信号（DQS）的延迟量。 第二调整电路能够以比第一调整电路更高的精度来调整选通信号（DQS）的延迟量。

公开(公告)号：US20150146477A1

公开(公告)日：2015-05-28

申请号：US14541589

申请日：2014-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaaki IIJIMA ,  Nguyen Thein

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G11C7/222

Abstract: In order to solve a problem that a calibration period for generating a signal obtained by delaying a core clock in a programmable manner is overhead in initialization, a clock generation circuit generates a plurality of delayed clocks having different phases by delaying a core clock which is an operation clock of a CPU, and selects a resynchronization clock whose phase is later than and closest to a phase of a data strobe signal from among the generated delayed clocks and the core clock.

Abstract translation: 为了解决用于产生通过以可编程方式延迟核心时钟而获得的信号的校准周期的初始化的开销的问题，时钟产生电路通过延迟核心时钟来产生具有不同相位的多个延迟时钟，该核心时钟是 并且从所生成的延迟时钟和核心时钟中选择相位晚于并且最接近于数据选通信号的相位的再同步时钟。

公开(公告)号：US20160164529A1

公开(公告)日：2016-06-09

申请号：US15043137

申请日：2016-02-12

Applicant: Renesas Electronics Corporation

Inventor： Takashi Nakamura ,  Kosuke YAYAMA ,  Masaaki IIJIMA

IPC: H03L7/099

CPC classification number: H03L7/0991 ,  H03L1/022 ,  H03L7/00 ,  H03L7/02 ,  H03L7/06 ,  H03L7/099 ,  H03L7/16 ,  H03L7/22 ,  H03L2207/06 ,  H03L2207/50

Abstract: A frequency-locked loop circuit includes a digital control oscillator that generates a clock, and an FLL (frequency-locked loop) controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock, and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock, the frequency comparison unit determines the frequency of the clock, and the delay code control unit generates the frequency control code according to a determination result of the frequency comparison unit, and outputs the frequency control code to the digital control oscillator.

Abstract translation: 锁频环路电路包括产生时钟的数字控制振荡器和产生用于控制时钟的振荡频率的频率控制码的FLL（锁频环路）控制器。 FLL控制器包括频率比较单元，其将由数字控制振荡器产生的时钟的频率与相乘的参考时钟的频率进行比较;以及延迟码控制单元，其基于频率比较单元的比较结果， 频率控制代码，使得由数字控制振荡器产生的时钟频率与倍增的参考时钟的频率相匹配，频率比较单元确定时钟的频率，并且延迟码控制单元根据 频率比较单元的确定结果，并将频率控制代码输出到数字控制振荡器。