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    FREQUENCY-LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
    2.
    发明申请
    FREQUENCY-LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    频率锁定环路和半导体集成电路

    公开(公告)号：US20160164529A1

    公开(公告)日：2016-06-09

    申请号：US15043137

    申请日：2016-02-12

    Applicant: Renesas Electronics Corporation

    Inventor： Takashi Nakamura ,  Kosuke YAYAMA ,  Masaaki IIJIMA

    IPC: H03L7/099

    CPC classification number: H03L7/0991 ,  H03L1/022 ,  H03L7/00 ,  H03L7/02 ,  H03L7/06 ,  H03L7/099 ,  H03L7/16 ,  H03L7/22 ,  H03L2207/06 ,  H03L2207/50

    Abstract: A frequency-locked loop circuit includes a digital control oscillator that generates a clock, and an FLL (frequency-locked loop) controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock, and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock, the frequency comparison unit determines the frequency of the clock, and the delay code control unit generates the frequency control code according to a determination result of the frequency comparison unit, and outputs the frequency control code to the digital control oscillator.

    Abstract translation: 锁频环路电路包括产生时钟的数字控制振荡器和产生用于控制时钟的振荡频率的频率控制码的FLL（锁频环路）控制器。 FLL控制器包括频率比较单元，其将由数字控制振荡器产生的时钟的频率与相乘的参考时钟的频率进行比较;以及延迟码控制单元，其基于频率比较单元的比较结果， 频率控制代码，使得由数字控制振荡器产生的时钟频率与倍增的参考时钟的频率相匹配，频率比较单元确定时钟的频率，并且延迟码控制单元根据 频率比较单元的确定结果，并将频率控制代码输出到数字控制振荡器。

    Frequency-locked loop circuit and semiconductor integrated circuit
    3.
    发明授权
    Frequency-locked loop circuit and semiconductor integrated circuit 有权
    锁相环电路和半导体集成电路

    公开(公告)号：US09276585B2

    公开(公告)日：2016-03-01

    申请号：US14244800

    申请日：2014-04-03

    Applicant: Renesas Electronics Corporation

    Inventor： Takashi Nakamura ,  Kosuke Yayama ,  Masaaki Iijima

    IPC: H03L7/099 ,  H03L1/02 ,  H03L7/02 ,  H03L7/06 ,  H03L7/00 ,  H03L7/16 ,  H03L7/22

    CPC classification number: H03L7/0991 ,  H03L1/022 ,  H03L7/00 ,  H03L7/02 ,  H03L7/06 ,  H03L7/099 ,  H03L7/16 ,  H03L7/22 ,  H03L2207/06 ,  H03L2207/50

    Abstract: A frequency-locked loop circuit has a digital control oscillator that generates a clock, and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller has a frequency comparison unit and a delay code control unit. The frequency comparison unit compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock. The delay code control unit generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit.

    Abstract translation: 锁频环路电路具有产生时钟的数字控制振荡器和产生用于控制时钟的振荡频率的频率控制码的FLL控制器。 FLL控制器具有频率比较单元和延迟码控制单元。 频率比较单元将由数字控制振荡器产生的时钟的频率与相乘的参考时钟的频率进行比较。 延迟码控制单元基于频率比较单元的比较结果生成频率控制码，使得由数字控制振荡器产生的时钟的频率与倍增的参考时钟的频率相匹配。 频率比较单元通过使用第一和第二阈值来确定时钟的频率。 延迟码控制单元根据频率比较单元的判定来生成频率控制码。

    Resistance correction circuit, resistance correction method, and semiconductor device
    4.
    发明授权
    Resistance correction circuit, resistance correction method, and semiconductor device 有权
    电阻校正电路，电阻校正方法和半导体器件

    公开(公告)号：US08970266B2

    公开(公告)日：2015-03-03

    申请号：US14066731

    申请日：2013-10-30

    Applicant: Renesas Electronics Corporation

    Inventor： Kosuke Yayama ,  Takashi Nakamura

    IPC: H01C13/02 ,  H01L49/02 ,  H01L27/08

    CPC classification number: G06F1/08 ,  H01C13/02 ,  H01L27/0802 ,  H01L28/20 ,  H03B5/24

    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

    Abstract translation: 公开了抑制应力诱导电阻值变化的半导体装置。 半导体器件包括电阻校正电路。 电阻校正电路包括其应力电阻值关系为第一关系的第一电阻器，其应力电阻值关系为第二关系的第二电阻器和控制校正目标电阻器的电阻值的校正部件。 校正部分检测第一电阻器的电阻值和第二电阻器的电阻值之间的差异，并根据检测结果校正校正目标电阻器的电阻值。

    RESISTANCE CORRECTION CIRCUIT, RESISTANCE CORRECTION METHOD, AND SEMICONDUCTOR DEVICE
    5.
    发明申请
    RESISTANCE CORRECTION CIRCUIT, RESISTANCE CORRECTION METHOD, AND SEMICONDUCTOR DEVICE 有权
    电阻校正电路，电阻校正方法和半导体器件

    公开(公告)号：US20150162874A1

    公开(公告)日：2015-06-11

    申请号：US14560013

    申请日：2014-12-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kosuke Yayama ,  Takashi Nakamura

    IPC: H03B5/24

    CPC classification number: G06F1/08 ,  H01C13/02 ,  H01L27/0802 ,  H01L28/20 ,  H03B5/24

    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

    Abstract translation: 公开了抑制应力诱导电阻值变化的半导体装置。 半导体器件包括电阻校正电路。 电阻校正电路包括其应力电阻值关系为第一关系的第一电阻器，其应力电阻值关系为第二关系的第二电阻器和控制校正目标电阻器的电阻值的校正部件。 校正部分检测第一电阻器的电阻值和第二电阻器的电阻值之间的差异，并根据检测结果校正校正目标电阻器的电阻值。

    RESISTANCE CORRECTION CIRCUIT, RESISTANCE CORRECTION METHOD, AND SEMICONDUCTOR DEVICE
    6.
    发明申请
    RESISTANCE CORRECTION CIRCUIT, RESISTANCE CORRECTION METHOD, AND SEMICONDUCTOR DEVICE 有权
    电阻校正电路，电阻校正方法和半导体器件

    公开(公告)号：US20140118060A1

    公开(公告)日：2014-05-01

    申请号：US14066731

    申请日：2013-10-30

    Applicant: Renesas Electronics Corporation

    Inventor： Kosuke Yayama ,  Takashi Nakamura

    IPC: H01L27/00

    CPC classification number: G06F1/08 ,  H01C13/02 ,  H01L27/0802 ,  H01L28/20 ,  H03B5/24

    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

    Abstract translation: 公开了抑制应力诱发电阻值变化的半导体装置。 该半导体器件包括电阻校正电路。 电阻校正电路包括其应力电阻值关系为第一关系的第一电阻器，其应力电阻值关系为第二关系的第二电阻器和控制校正目标电阻器的电阻值的校正部件。 校正部分检测第一电阻器的电阻值和第二电阻器的电阻值之间的差异，并根据检测结果校正校正目标电阻器的电阻值。

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