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公开(公告)号：US20140239988A1
公开(公告)日：2014-08-28
申请号：US14184230
申请日：2014-02-19
Applicant: Renesas Electronics Corporation
Inventor： Osamu SOMA
IPC: G01R31/28
CPC classification number: G01R31/31715 , G01R31/2851
Abstract: A semiconductor device includes: a drive circuit; a standby circuit; and a detection circuit. The drive circuit turns on an output transistor connected to a load based on an active input signal. The standby circuit intermittently outputs an output signal based on a non-active input signal. The detection circuit measures voltage of a load side of the output transistor based on the output signal and output a measurement result.
Abstract translation: 半导体器件包括：驱动电路; 备用电路; 和检测电路。 驱动电路基于有源输入信号接通连接到负载的输出晶体管。 备用电路基于非有效输入信号间歇地输出输出信号。 检测电路基于输出信号测量输出晶体管的负载侧的电压，并输出测量结果。
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公开(公告)号：US20160365721A1
公开(公告)日：2016-12-15
申请号：US15141676
申请日：2016-04-28
Applicant: Renesas Electronics Corporation
Inventor： Osamu SOMA , Akira UEMURA
CPC classification number: G07C9/00182 , B60Q11/005 , F02N11/0807 , G07C9/00309 , H01L2224/48247 , H01L2224/49171 , H01L2924/181 , H03K19/017509 , H05B33/0815 , H05B33/089 , Y02B20/341 , H01L2924/00012
Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.
Abstract translation: 提供了一种复杂的半导体器件。 包括一个包装中的IPD芯片和MCU芯片的半导体器件。 IPD芯片包括：驱动外部负载的功率晶体管; 驱动功率晶体管的栅极驱动电路; 以及保护功率晶体管不发生故障的保护电路。 MCU芯片包括：运算处理单元，其基于从保护电路输出的检测数据进行运算处理;以及存储单元，存储用于运算处理单元的程序。 MCU芯片具有根据检测到的数据来控制功率晶体管的操作的功能。
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Patent Agency Ranking
公开(公告)号：US20160093557A1
公开(公告)日：2016-03-31
申请号：US14871769
申请日：2015-09-30
Applicant: Renesas Electronics Corporation
Inventor： Atsushi NISHIKIZAWA , Tadatoshi DANNO , Hiroyuki NAKAMURA , Osamu SOMA , Akira UEMURA
IPC: H01L23/495 , H01L25/065 , H01L23/58 , H01L23/31
CPC classification number: H01L23/49503 , H01L23/3114 , H01L23/4952 , H01L23/49562 , H01L23/49575 , H01L23/585 , H01L25/0655 , H01L2224/05554 , H01L2224/32245 , H01L2224/33505 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48111 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903 , H01L2224/73265 , H01L2224/92247 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.
Abstract translation: 半导体器件包括第一和第二半导体芯片，多个引线，多个引线和密封这些部件的密封体。 电连接到第一和第二电极焊盘的第一焊盘电极，第二焊盘电极和内部布线形成在第一半导体芯片的主表面上。 第二半导体芯片的第三焊盘电极经由第一导线电连接到第一半导体芯片的第一电极焊盘，第一半导体芯片的第二电极焊盘经由第二导线电连接到第一引线。 第一引线和第一半导体芯片之间的距离小于第一引线和第二半导体芯片之间的距离。 第一电极焊盘，第二电极焊盘和内部布线不连接到形成在第一半导体芯片中的任何电路。
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公开(公告)号：US20180080963A1
公开(公告)日：2018-03-22
申请号：US15823217
申请日：2017-11-27
Applicant: Renesas Electronics Corporation
Inventor： Osamu SOMA , Akira Uemura , Kenji Amada
Abstract: A control method of a semiconductor device includes inspecting an electrical property of a current detection circuit in the first semiconductor chip, writing information on a correction equation obtained on the basis of an inspection result in a memory circuit of the second semiconductor chip, and correcting, with the second semiconductor chip, a detection result obtained by the current detection circuit on the basis of the information on the correction equation.
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公开(公告)号：US20200091714A1
公开(公告)日：2020-03-19
申请号：US16554207
申请日：2019-08-28
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Naohiro YOSHIMURA , Osamu SOMA
Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.
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公开(公告)号：US20200028503A1
公开(公告)日：2020-01-23
申请号：US16452205
申请日：2019-06-25
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Osamu SOMA
IPC: H03K17/0412 , H03K17/16 , H02J7/00
Abstract: A semiconductor device and electronic control device capable of shutting off the reverse current flow from a load to a power supply is provided.The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the load-driving terminal Po2(+), and has a source and a back-gate coupled to the positive power supply terminal Pi2(+). The power transistor QN2 is provided in series with the power transistor QN1, and its sources and backgates are coupled to the load-driving terminal Po2(+). The booster CP1a charges the gates of the power transistors QN1. The gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source when the potential of the negative power supply terminal Pi2(−) is higher than the potential of the positive power supply terminal Pi2(+).
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7.发明申请公开(公告)号：US20160305989A1
公开(公告)日：2016-10-20
申请号：US15068929
申请日：2016-03-14
Applicant: Renesas Electronics Corporation
Inventor： Osamu SOMA , Akira Uemura , Kenji Amada
Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.
Abstract translation: 提供具有高精度电流检测功能的半导体器件。 使用其中两个半导体芯片安装在一个封装中的半导体器件进行电流检测。 第一半导体芯片设置有经由负载驱动端子向负载供电的电源晶体管，以及用于检测流过负载驱动端子的电流的电流检测电路。 在半导体器件的检查过程中，检查第一半导体芯片中的电流检测电路的电特性，并将作为检查结果获得的校正方程的信息写入第二半导体芯片的存储电路。 第二半导体芯片基于关于写入有关存储器电路的校正方程的信息来校正由电流检测电路获得的检测结果。
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