公开(公告)号：US20190341339A1

公开(公告)日：2019-11-07

申请号：US16380651

申请日：2019-04-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoki FUJITA ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H02M1/34 ,  H03K17/0814 ,  H02M3/335 ,  H01L29/78 ,  H01L23/00

Abstract: Reliability of a semiconductor device is improved. In the semiconductor device SA1, a snubber capacitor pad SNP electrically connected to the capacitor electrode of the snubber capacitor is formed on the surface of the semiconductor chip CHP.

公开(公告)号：US20210118781A1

公开(公告)日：2021-04-22

申请号：US17060545

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazunori HASEGAWA ,  Yuichi YATO ,  Hiroyuki NAKAMURA ,  Yukihiro SATO ,  Hiroya SHIMOYAMA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.

公开(公告)号：US20180182692A1

公开(公告)日：2018-06-28

申请号：US15826815

申请日：2017-11-30

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H02P27/06 ,  H01L2924/00012

Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.

公开(公告)号：US20140061821A1

公开(公告)日：2014-03-06

申请号：US13973077

申请日：2013-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenya KAWANO ,  Hiroyuki NAKAMURA ,  Yukihiro SATO

IPC: H01L23/373 ,  H01L29/772

CPC classification number: H01L23/373 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L29/772 ,  H01L29/7813 ,  H01L2224/05553 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.

Abstract translation: 提供一种具有半导体器件和安装板的电子器件。 半导体器件具有管芯焊盘，管芯焊盘上的半导体芯片，将管芯焊盘连接到半导体芯片的耦合部件以及覆盖半导体芯片的上部和管芯焊盘侧表面的半导体封装件。 在该半导体器件中，将安装板耦合到管芯焊盘的耦合部件的平面面积小于从半导体封装材料露出的裸片焊盘的下表面的平面面积。 这使得可以减少由于存在于管芯焊盘和半导体芯片之间的耦合部件的温度循环而导致的芯片焊盘和半导体芯片之间的分离。

公开(公告)号：US20180218969A1

公开(公告)日：2018-08-02

申请号：US15850009

申请日：2017-12-21

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki NAKAMURA ,  Hiroya SHIMOYAMA

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L27/06 ,  H01L29/66 ,  H02P27/06 ,  H02M7/00 ,  H02M7/537

CPC classification number: H01L23/49575 ,  B62D5/0406 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0655 ,  H01L27/0629 ,  H01L29/66992 ,  H01L29/78 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/09165 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/40499 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/49179 ,  H01L2224/49505 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83862 ,  H01L2224/84801 ,  H01L2224/84862 ,  H01L2224/85013 ,  H01L2224/92246 ,  H01L2224/92247 ,  H02M7/003 ,  H02M7/537 ,  H02P27/06 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/01047

Abstract: The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

公开(公告)号：US20170221800A1

公开(公告)日：2017-08-03

申请号：US15515297

申请日：2015-03-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NISHIKIZAWA ,  Yuichi YATO ,  Hiroi OKA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

公开(公告)号：US20160093557A1

公开(公告)日：2016-03-31

申请号：US14871769

申请日：2015-09-30

Applicant: Renesas Electronics Corporation

Inventor： Atsushi NISHIKIZAWA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA ,  Osamu SOMA ,  Akira UEMURA

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/58 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract translation: 半导体器件包括第一和第二半导体芯片，多个引线，多个引线和密封这些部件的密封体。 电连接到第一和第二电极焊盘的第一焊盘电极，第二焊盘电极和内部布线形成在第一半导体芯片的主表面上。 第二半导体芯片的第三焊盘电极经由第一导线电连接到第一半导体芯片的第一电极焊盘，第一半导体芯片的第二电极焊盘经由第二导线电连接到第一引线。 第一引线和第一半导体芯片之间的距离小于第一引线和第二半导体芯片之间的距离。 第一电极焊盘，第二电极焊盘和内部布线不连接到形成在第一半导体芯片中的任何电路。

公开(公告)号：US20180315685A1

公开(公告)日：2018-11-01

申请号：US16020353

申请日：2018-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NISHIKIZAWA ,  Yuichi YATO ,  Hiroi OKA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

公开(公告)号：US20190088577A1

公开(公告)日：2019-03-21

申请号：US16048284

申请日：2018-07-29

Applicant: Renesas Electronics Corporation

Inventor： Hiroya SHIMOYAMA ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H05K7/20

Abstract: Performance of a semiconductor device is enhanced. A semiconductor device is a semiconductor device obtained by sealing in a sealing portion first, second, and third semiconductor chips each incorporating a power transistor for high-side switch, fourth, fifth, and sixth semiconductor chips each incorporating a power transistor for low-side switch, and a semiconductor chip incorporating a control circuit controlling these chips. The source pads of the fourth, fifth, and sixth semiconductor chips are electrically coupled to a plurality of leads LD9 and a plurality of leads LD10 via a metal plate. As viewed in a plane, the leads LD9 intersect with a side MRd4 of the sealing portion and the leads LD10 intersect with a side MRd2 of the sealing portion.

公开(公告)号：US20130043576A1

公开(公告)日：2013-02-21

申请号：US13655446

申请日：2012-10-19

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki NAKAMURA ,  Atsushi FUJIKI ,  Tatsuhiro SEKI ,  Nobuya KOIKE ,  Yukihiro SATO ,  Kisho ASHIDA

IPC: H01L23/495

CPC classification number: H01L27/07 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/66 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.

Abstract translation: 提高半导体器件的性能和可靠性。 对于半导体芯片CP1，用于开关的功率MOSFET Q1和Q2，用于检测功率MOSFET Q1的发热的二极管DD1，用于检测功率MOSFET Q2的发热的二极管DD2和多个焊盘电极PD 。 功率MOSFET Q1和二极管DD1布置在侧面SD1侧的第一MOSFET区域RG1中，功率MOSFET Q2和二极管DD2布置在侧面SD2侧的第二MOSFET区RG2中。 二极管DD1沿着侧面SD1配置，二极管DD2沿着侧面SD2配置，除了用于源极的焊盘电极PDS1和PDS2以外的所有焊盘电极PD沿着二极管DD1和DD2之间的侧面SD3排列。