公开(公告)号：US20180151460A1

公开(公告)日：2018-05-31

申请号：US15879610

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L23/66

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20170236789A1

公开(公告)日：2017-08-17

申请号：US15585468

申请日：2017-05-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko OCHIAI

IPC: H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/528 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/585 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311

Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.

公开(公告)号：US20170213776A1

公开(公告)日：2017-07-27

申请号：US15515465

申请日：2014-12-24

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20140167286A1

公开(公告)日：2014-06-19

申请号：US14077503

申请日：2013-11-12

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko OCHIAI

IPC: H01L23/522

CPC classification number: H01L23/585 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311

Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.

Abstract translation: 半导体器件包括穿透硅衬底的TSV。 密封环从最接近硅衬底的第一低相对介电常数膜提供到离硅衬底最远的第二低相对介电常数薄膜。 密封环形成为从晶片正面在硅基板上以鸟瞰的方式包围TSV。 这实现了包括低相对介电常数膜和TSV的半导体器件中的低相对介电常数膜中的裂纹的产生或进展的抑制。