-
1.发明授权Method of fabricating MOS transistors using selective polysilicon deposition 失效使用选择性聚硅氧烷沉积制造MOS晶体管的方法
公开(公告)号：US5082794A
公开(公告)日：1992-01-21
申请号：US569097
申请日：1990-08-17
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66583 , H01L29/1033 , H01L29/1045 , H01L29/66553 , H01L29/7836 , H01L29/66537 , Y10S148/122
摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.
摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 该结构可以用作导致形成由一次侧壁间隔物形成的逆T晶体管或常规LDD结构的工艺的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。
-
公开(公告)号：US4984042A
公开(公告)日：1991-01-08
申请号：US309589
申请日：1989-02-13
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/66553 , H01L29/7836 , H01L29/66537
摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.
摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 这种结构可以用作导致逆T晶体管或由一次性侧壁间隔物形成的常规LDD结构的过程的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。
-
公开(公告)号：US5358890A
公开(公告)日：1994-10-25
申请号：US47933
申请日：1993-04-19
IPC分类号： H01L21/32 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76216 , H01L21/32
摘要： A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be constructed from a variety of materials including silicon nitride, silicon oxynitride, boron nitride, polysilicon, and germanium oxide. Thick isolation regions (20) are formed on either side of the isolation mask (15) and an ion implant process is carried out to form doped regions (22) in the substrate (10) immediately below the isolation regions (20). The isolation mask (15) prevents dopant atoms (24) from entering the active region (16) of the substrate (10).
摘要翻译： 一种用于形成具有通过将掺杂剂原子（24）通过隔离区域（22）注入而形成的自对准通道 - 停止（22）的隔离区域（20）的工艺。 隔离掩模（15）形成在半导体衬底（10）中的有源区（16）上。 隔离掩模可以由各种材料构成，包括氮化硅，氮氧化硅，氮化硼，多晶硅和氧化锗。 在隔离掩模（15）的任一侧上形成厚隔离区（20），并且执行离子注入工艺以在隔离区（20）正下方的衬底（10）中形成掺杂区（22）。 隔离掩模（15）防止掺杂剂原子（24）进入衬底（10）的有源区（16）。
-
公开(公告)号：US4948745A
公开(公告)日：1990-08-14
申请号：US353933
申请日：1989-05-22
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/41783 , H01L29/665 , H01L29/66537 , H01L29/66545
摘要： A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes.
摘要翻译： 公开了用于制造升高的源极/漏极IGFET器件的工艺。 根据该方法的一个实施例，提供了硅衬底，其通过场氧化物被分为有源场和场区。 在有源区上形成栅极氧化物，并且在栅极氧化物上沉积多晶硅薄层和氮化硅层。 蚀刻多晶硅和氮化硅以形成堆叠结构，其中间隔物与栅电极的图案中具有与层叠结构基本相同的高度。 在层叠结构的边缘上形成侧壁间隔物，并去除氮化硅。 然后将多晶硅沉积到多晶硅和源极和漏极区域的暴露部分上以完成栅极电极并形成源极和漏极。 选择性沉积的多晶硅从源区和漏区向上延伸到场氧化物上。 侧壁间隔件提供栅电极和相邻的源漏电极之间的物理和电隔离。
-
公开(公告)号：US4942137A
公开(公告)日：1990-07-17
申请号：US393210
申请日：1989-08-14
IPC分类号： H01L21/308 , H01L21/32 , H01L21/762 , H01L21/763
CPC分类号： H01L21/32 , H01L21/3086 , H01L21/76235 , H01L21/763
摘要： A method for fabricating a self-aligned trench structure in a semiconductor device is disclosed. In accordance with one method for fabricating the trench structure, an oxidation resistant material having an opening is used as a masking layer. The edge of the opening in the masking layer is covered by a sidewall spacer which protects a portion of the substrate from attack by the etchant used to form the trench. The trench is filled with a trench fill material by selective deposition using a seeding material formed on the sidewall of the trench as a nucleation site. After the trench is filled, the sidewall spacer is removed and the underlying substrate is oxidized to form an electrical insulation region around the upper portion of the trench. The mask layer is removed and the remaining substrate is doped using the insulation region surrounding the trench as a dopant mask.
摘要翻译： 公开了一种在半导体器件中制造自对准沟槽结构的方法。 根据制造沟槽结构的一种方法，使用具有开口的抗氧化材料作为掩模层。 掩模层中的开口的边缘由侧壁间隔物覆盖，该侧壁间隔件保护衬底的一部分免受用于形成沟槽的蚀刻剂的侵蚀。 通过使用形成在沟槽的侧壁上的接种材料作为成核位置通过选择性沉积来填充沟槽填充材料。 在填充沟槽之后，去除侧壁间隔物，并且将下面的衬底氧化以在沟槽的上部周围形成电绝缘区域。 去除掩模层，并且使用围绕沟槽的绝缘区域作为掺杂剂掩模来掺杂剩余的衬底。
-
公开(公告)号：US4978626A
公开(公告)日：1990-12-18
申请号：US240013
申请日：1988-09-02
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/823828 , H01L29/78 , H01L29/7836 , H01L27/0928
摘要： An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.
摘要翻译： 通过使用确保栅极氧化物层不会被无意蚀刻而不被静电电荷破裂的工艺形成LDD晶体管。 在半导体衬底之上的栅极氧化物层上形成具有不同掺杂水平的至少两个厚度的栅电极材料。 使用化学蚀刻，其中通过监测化学蚀刻反应的化学产品和化学反应物的比例，可以容易地检测到栅电极材料的蚀刻中的特定端点。 在离子注入期间允许一小层栅电极材料保留在栅极氧化物层上方，并且在制造LDD晶体管时形成和去除栅极侧壁间隔物。 在形成大多数LDD晶体管之后，去除栅电极材料的剩余保护厚度，暴露的栅极氧化层暴露于最后的氧化退火步骤。 在其他形式中，形成逆T栅极结构LDD晶体管，并且通过具有减少数量的离子注入步骤的工艺形成LDD晶体管。
-
公开(公告)号：US4852062A
公开(公告)日：1989-07-25
申请号：US101875
申请日：1987-09-28
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/105 , H01L27/115 , H01L27/11543 , H01L29/7885
摘要： An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.
摘要翻译： 具有浮动栅极和控制栅极的可擦除可编程只读存储器（EPROM）单元，其中浮置栅极和控制栅极与衬底中的源极/漏极/漏极/源极区域有意地偏移或不对称。 在编程期间，源极区域是与栅极间隔开的区域，而漏极区域与栅极对准。 该方向产生高栅极电流以提供更快的编程。 在读取操作期间，对准区域现在变为源极，并且间隔开的区域变为漏极以提供用于快速访问的高漏极电流。 本发明的非对称EPROM单元可以使用传统的间隔技术容易地制成。
-
公开(公告)号：US4811066A
公开(公告)日：1989-03-07
申请号：US109658
申请日：1987-10-19
申请人： James R. Pfiester , Frank K. Baker
发明人： James R. Pfiester , Frank K. Baker
CPC分类号： H01L29/4983 , Y10S257/903
摘要： A compact, multi-state field effect transistor (FET) cell having a gate with edge portions of a different conductivity type than a central portion of the gate. Both the edge portions and the central portion extend from the source to the drain of the multi-state FET device. This device would have two different threshold voltages (V.sub.T), one where the central portion would turn on first, followed by the edges for the entire gate width to be active to give a second level of current flow. Such devices would be useful in building very compact or high density multi-state read-only-memories (ROMs).
摘要翻译： 一种紧凑的多态场效应晶体管（FET）单元，其具有栅极，该栅极具有与栅极的中心部分不同的导电类型的边缘部分。 边缘部分和中心部分都从多态FET器件的源极延伸到漏极。 该装置将具有两个不同的阈值电压（VT），其中中心部分首先接通，然后是使整个栅极宽度的边缘有效以产生第二电流。 这样的设备在构建非常紧凑或高密度多状态只读存储器（ROM）中将是有用的。
-
公开(公告)号：US5352631A
公开(公告)日：1994-10-04
申请号：US991801
申请日：1992-12-16
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/283
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/66575 , H01L29/6659 , H01L29/66628 , H01L21/2257 , H01L29/66545
摘要： A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.
摘要翻译： 用于形成晶体管（10）的工艺通过提供衬底（12）开始。 场氧化物区域（14）或等效隔离形成在衬底（12）之上或之内。 形成栅极氧化物（16）和导电层（18）。 形成覆盖导电层（18）的掩模层（20）。 蚀刻掩模层（20）和导电层（18）以形成栅电极并限定漏区（19）和源极区（21）。 隔板（22）形成在栅电极附近。 在源极和漏极区（分别为21和19）上形成第一硅化区（26）。 掩模层防止栅电极硅化。 去除掩模层（20），并且形成覆盖栅电极的第二硅化区域（30）。 第二硅化物区域（30）和硅化物区域（26）由不同的硅化物制成。
-
公开(公告)号：US5319232A
公开(公告)日：1994-06-07
申请号：US76488
申请日：1993-06-14
申请人： James R. Pfiester
发明人： James R. Pfiester
IPC分类号： H01L21/225 , H01L21/331 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/10 , H01L29/72
CPC分类号： H01L29/66628 , H01L21/2257 , H01L21/823814 , H01L29/66287 , H01L29/66492 , H01L29/6653 , Y10S257/90
摘要： A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).
摘要翻译： 一种晶体管（10或11）及其形成方法。 晶体管（10）具有基板（12）。 衬底（12）具有覆盖在电介质层（14）上的上覆电介质层（14）和绝缘导电控制电极（16）。 电介质区域（18）覆盖绝缘导电控制电极（16），电介质区域（20）与绝缘导电控制电极（16）相邻。 间隔物（30）与电介质区域（20）相邻。 外延区域（24）与间隔物（30）相邻，并且间隔物（30）覆盖外延区域（24）的部分。 电介质区域（26）覆盖在外延区域（24）上。 高掺杂源极和漏极区域（32）位于外延区域（24）的下面。 位于间隔物（30）下方的LDD区域（28）与源区和漏区（32）相邻并电连接。
-
-
-
-
-
-
-
-
-
搜索结果
67 条记录 (耗时 0.022 秒)
