利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.031 秒)

    FABRICATION OF SINGLE-CRYSTALLINE GRAPHENE ARRAYS
    2.
    发明申请
    FABRICATION OF SINGLE-CRYSTALLINE GRAPHENE ARRAYS 有权
    单晶石墨阵列的制造

    公开(公告)号：US20120088039A1

    公开(公告)日：2012-04-12

    申请号：US13270766

    申请日：2011-10-11

    申请人： Qingkai Yu ,  Shin-Shem Pei

    发明人： Qingkai Yu ,  Shin-Shem Pei

    IPC分类号： C23C14/30

    CPC分类号： B82Y40/00 ,  B82Y30/00 ,  C01B32/186 ,  C01B2204/32

    摘要： The present disclosure demonstrates the synthesis of ordered arrays of GSC's by re-growth from pre-patterned seed crystals, offering an approach for scalable fabrication of single crystal graphene devices while avoiding domain boundaries. Each graphene island is a single crystal and every graphene island is of similar size. The size of graphene island arrays can be as small as less than 1 mm2 or as large as several m2. The distance between each GSC island is also adjustable from several micrometers to millimeters. All of the graphene islands are addressable for devices and electrical circuit fabrication.

    摘要翻译： 本公开内容展示了通过从预先图案化的晶种再生长来合成GSC的有序阵列，为避免畴边界提供了可扩展制造单晶石墨烯器件的方法。 每个石墨烯岛是单晶，每个石墨烯岛的大小相似。 石墨烯岛阵列的尺寸可以小至小于1mm2或大至几平方米。 每个GSC岛之间的距离也可以从几微米到毫米。 所有的石墨烯岛可寻址器件和电路制造。

    Josephson device fabrication method
    3.
    发明授权
    Josephson device fabrication method 失效
    约瑟夫逊器件制造方法

    公开(公告)号：US4470190A

    公开(公告)日：1984-09-11

    申请号：US445290

    申请日：1982-11-29

    申请人： Theodore A. Fulton ,  Shin-Shem Pei

    发明人： Theodore A. Fulton ,  Shin-Shem Pei

    IPC分类号： H01L39/24 ,  H01L39/22 ,  H01L21/265

    CPC分类号： H01L39/2493 ,  Y10S505/922

    摘要： A method for changing Josephson device parameters, e.g., the critical current of a Josephson junction. The method comprises incorporating doping material into the device, or part of the device, followed by a light anneal. Exemplary dopants include In, Sn, Sb, Te, Bi, Hg, Mg, Li, Cd, Na and Ta, with In, Sn, and Sb being preferred dopants for changing the critical current of a Josephson junction having a Pb-containing counter electrode. The dopant can be incorporated into the device by in-diffusion after deposition onto the surface, by ion implantation, or by any other convenient method. The amount of dopant required is typically small. For example, deposition of a Sn layer of 0.05 nm effective thickness onto the 200 nm thick Pb-Sb(1.5 wt. %) counter electrode of a cross-type Josephson junction, and annealing at 80.degree. C. for about 3 hours, resulted in an increase in the critical current of the junction by a factor of about 2.5. The method is considered to have wide applicability in the manufacture of Josephson devices, and can be applied globally, i.e., to all the devices on a wafer or chip, or locally, i.e., to selected devices.

    摘要翻译： 一种用于改变约瑟夫逊器件参数的方法，例如约瑟夫逊结的临界电流。 该方法包括将掺杂材料掺入器件或器件的一部分，随后进行轻退火。 示例性的掺杂剂包括In，Sn，Sb，Te，Bi，Hg，Mg，Li，Cd，Na和Ta，其中In，Sn和Sb是用于改变具有含Pb计数器的约瑟夫逊结的临界电流的优选掺杂剂 电极。 通过在表面上沉积后，通过离子注入或通过任何其它方便的方法，掺杂剂可以通过扩散进入装置。 所需的掺杂剂的量通常很小。 例如，将0.05nm有效厚度的Sn层沉积到交叉型约瑟夫逊结的200nm厚的Pb-Sb（1.5重量％）对电极上，并在80℃退火约3小时，得到 在连接的临界电流增加约2.5倍。 该方法被认为在约瑟夫逊器件的制造中具有广泛的应用，并且可以全局地应用于晶片或芯片上的所有器件，或局部应用于所选器件。

    Method for making self-electro-optical device and devices made thereby
    5.
    发明授权
    Method for making self-electro-optical device and devices made thereby 失效
    由此制造自电光器件和器件的方法

    公开(公告)号：US5298454A

    公开(公告)日：1994-03-29

    申请号：US969685

    申请日：1992-10-30

    申请人： Lucian A. D'Asaro ,  Jenn-Ming Kuo ,  Shin-Shem Pei

    发明人： Lucian A. D'Asaro ,  Jenn-Ming Kuo ,  Shin-Shem Pei

    IPC分类号： G02F1/21 ,  G02F3/02 ,  H01L21/203

    CPC分类号： G02F3/028 ,  G02F1/218

    摘要： Applicants have discovered a method of reproducibly fabricating SEED devices having an enhanced contrast ratio by adjusting the thickness of a cap layer in relation to the reflector stacks to form a Fabry-Perot cavity. Specifically, after growth of the reflector stack and the quantum wells, the optical thickness of the region above reflector stacks is measured without breaking vacuum, and based on such measurement a cap layer is grown of sufficient thickness to form a Fabry-Perot cavity for light of desired wavelength. The result is a device with enhanced contrast between the "on" and "off" states sufficiently so that the state can be directly read without differential processing.

    摘要翻译： 申请人已经发现了通过相对于反射器叠层调节盖层的厚度以形成法布里 - 珀罗腔，已经发现了可重复地制造具有增强对比度的SEED装置的方法。 具体地说，在反射器堆叠和量子阱生长之后，在不破坏真空的情况下测量反射器叠层上方区域的光学厚度，并且基于这种测量，盖层生长足够的厚度以形成用于光的法布里 - 珀罗腔 的所需波长。 结果是充分地在“开”和“关”状态之间具有增强的对比度的装置，使得可以在不进行差分处理的情况下直接读取状态。

    Planar quantum well photodetector
    6.
    发明授权
    Planar quantum well photodetector 失效
    平面量子阱光电探测器

    公开(公告)号：US5281542A

    公开(公告)日：1994-01-25

    申请号：US36799

    申请日：1993-03-25

    申请人： Sanghee P. Hui ,  Shin-Shem Pei

    发明人： Sanghee P. Hui ,  Shin-Shem Pei

    IPC分类号： H01L31/10 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/18

    CPC分类号： B82Y20/00 ,  H01L31/022408 ,  H01L31/035236 ,  H01L31/184 ,  Y02E10/544 ,  Y02P70/521

    摘要： Using ion implant isolation, applicant has demonstrated a substantially planar quantum well photodetector free of exposed mesa side walls and having performance characteristics comparable with conventional mesa QWIPs. The planar photodetector presents a topography well suited for integration with other electronic components and the planar structure can be scaled to diameters much smaller than are typically useful in the conventional bonded devices.

    摘要翻译： 使用离子注入隔离，申请人已经证明了一种基本上平面的量子阱光电探测器，没有暴露的台面侧壁，具有与常规台面QWIP相当的性能特征。 平面光电检测器呈现出非常适合于与其它电子部件集成的形貌，并且平面结构可以缩放到比通常用于常规粘合装置的直径更小的直径。

    Fabrication of single-crystalline graphene arrays
    7.
    发明授权
    Fabrication of single-crystalline graphene arrays 有权
    单晶石墨烯阵列的制造

    公开(公告)号：US08597738B2

    公开(公告)日：2013-12-03

    申请号：US13270766

    申请日：2011-10-11

    申请人： Qingkai Yu ,  Shin-Shem Pei

    发明人： Qingkai Yu ,  Shin-Shem Pei

    IPC分类号： C23C14/30

    CPC分类号： B82Y40/00 ,  B82Y30/00 ,  C01B32/186 ,  C01B2204/32

    摘要： The synthesis of ordered arrays of GSC's by re-growth from pre-patterned seed crystals that offer an approach for scalable fabrication of single crystal graphene devices while avoiding domain boundaries is demonstrated herein. Each graphene island is a single crystal and every graphene island is of similar size. The size of graphene island arrays can be as small as less than 1 mm2 or as large as several m2. The distance between each GSC island is also adjustable from several micrometers to millimeters. All of the graphene islands are addressable for devices and electrical circuit fabrication.

    摘要翻译： 本文证明了通过从提供单晶石墨烯器件的可扩展制造方法提供方法的预先图案化的晶种再生长来合成GSC的有序阵列。 每个石墨烯岛是单晶，每个石墨烯岛的大小相似。 石墨烯岛阵列的尺寸可以小至小于1mm2或大至几平方米。 每个GSC岛之间的距离也可以从几微米到毫米。 所有的石墨烯岛可寻址器件和电路制造。