公开(公告)号：US4845050A

公开(公告)日：1989-07-04

申请号：US121183

申请日：1987-11-16

申请人： Manjin J. Kim ,  Dale M. Brown ,  Simon S. Cohen ,  Bernard Gorowitz ,  Richard J. Saia

发明人： Manjin J. Kim ,  Dale M. Brown ,  Simon S. Cohen ,  Bernard Gorowitz ,  Richard J. Saia

IPC分类号： H01L21/285 ,  H01L21/768

CPC分类号： H01L21/28512 ,  H01L21/76879 ,  Y10S148/003

摘要： A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon to a temperature in the range of 600.degree. C. to 650.degree. C. in a reducing atmosphere to form a low resistance contact.

摘要翻译： 将由钛和钨的合金的第一导体和诸如钼的难熔金属的第二导体组成的导电构件烧结到硅的导电构件至600℃至650℃的温度。 在还原气氛中形成低电阻接触。

公开(公告)号：US4444618A

公开(公告)日：1984-04-24

申请号：US471617

申请日：1983-03-03

申请人： Richard J. Saia ,  Bernard Gorowitz

发明人： Richard J. Saia ,  Bernard Gorowitz

IPC分类号： C23F4/00 ,  C23F1/12 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  C23F1/02 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/02071

摘要： A method and gas mixture of boron trichloride, carbon tetrachloride and oxygen useful for the reactive ion etching of aluminum and aluminum alloys to form metallizations for microelectronic devices and circuits is provided. The method and gas mixture provide consistent induction periods, high etch rates, high selectivity between photoresist and silicon dioxide, and minimal loading effects with good dimensional control. Also provided is a two step, two gas mixture process particularly useful in preventing linewidth loss due to excessive resist erosion during long overetches wherein the boron trichloride, carbon tetrachloride and oxygen gas mixture is used for etching and subsequently a boron trichloride-oxygen gas mixture is used for the overetch.

摘要翻译： 提供了用于铝和铝合金的反应离子蚀刻的三氯化硼，四氯化碳和氧气的方法和气体混合物，以形成用于微电子器件和电路的金属化。 该方法和气体混合物提供一致的诱导期，高蚀刻速率，光致抗蚀剂和二氧化硅之间的高选择性，以及具有良好尺寸控制的最小负载效应。 还提供两步二气混合方法，其特别可用于防止在长时间过蚀刻过程中过度的抗蚀剂侵蚀引起的线宽损失，其中使用三氯化硼，四氯化碳和氧气混合物进行蚀刻，随后将三氯化硼 - 氧气混合物 用于overetch。

公开(公告)号：US4824802A

公开(公告)日：1989-04-25

申请号：US104002

申请日：1987-10-02

申请人： Dale M. Brown ,  Bernard Gorowitz ,  Richard J. Saia

发明人： Dale M. Brown ,  Bernard Gorowitz ,  Richard J. Saia

IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L21/312

CPC分类号： H01L21/7684 ,  H01L21/76877

摘要： A method compatible with very large scale integrated circuit fabrication processes is employed to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal such as molybdenum or tungsten is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug conductive layers. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition. The process and structure provided herein significantly alleviates step coverage problems associated with aluminum and like materials which do not readily penetrate small VLSI circuit openings.

摘要翻译： 采用与大规模集成电路制造工艺兼容的方法来提供由集成电路器件中的绝缘层隔开的导电层之间的电连接。 通过一种或多种方法沉积诸如钼或钨的中间金属，以便填充绝缘层中的开口。 可以在衬底上施加平坦化抗蚀剂，并将所得结构平坦化地蚀刻到绝缘层上，以提供金属插头导电层。 通过溅射，蒸发或通过选择性或非选择性化学气相沉积沉积。 本文提供的方法和结构显着地减轻了与不容易穿透小型VLSI电路开口的铝和类似材料相关的步骤覆盖问题。

公开(公告)号：US5524339A

公开(公告)日：1996-06-11

申请号：US308886

申请日：1994-09-19

申请人： Bernard Gorowitz ,  Richard J. Saia ,  Kevin M. Durocher

发明人： Bernard Gorowitz ,  Richard J. Saia ,  Kevin M. Durocher

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H05K3/30

CPC分类号： H01L23/562 ,  H01L23/29 ,  H01L23/315 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T29/49144 ,  Y10T29/49146

摘要： In a method for preserving an air bridge structure on an integrated circuit chip, a protective layer is plasma-deposited over the top and sides of the air bridge. A high density interconnect structure is applied over the chip and protective layer. The protective film provides mechanical strength during the application of the high density interconnect structure to prevent deformation. It also prevents any contamination from intruding under the air bridge. More importantly, the protective film only negligibly impedes the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure.

摘要翻译： 在一种用于在集成电路芯片上保持空气桥结构的方法中，保护层被等离子体沉积在空气桥的顶部和侧面上。 在芯片和保护层上施加高密度互连结构。 保护膜在应用高密度互连结构期间提供机械强度以防止变形。 它还可以防止任何污染物侵入空气桥下。 更重要的是，保护膜只能忽略不计地阻碍空气桥的性能，因此不需要去除，从而消除了消除HDI结构的必要性。

公开(公告)号：US4871617A

公开(公告)日：1989-10-03

申请号：US595800

申请日：1984-04-02

申请人： Manjin J. Kim ,  Dale M. Brown ,  Simon S. Cohen ,  Bernard Gorowitz ,  Richard J. Saia

发明人： Manjin J. Kim ,  Dale M. Brown ,  Simon S. Cohen ,  Bernard Gorowitz ,  Richard J. Saia

IPC分类号： H01L21/285 ,  H01L21/768

CPC分类号： H01L21/28512 ,  H01L21/76879 ,  Y10T428/12528 ,  Y10T428/12597 ,  Y10T428/12826 ,  Y10T428/1284

摘要： A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon of low resistivity to form a low resistance contact therewith.

摘要翻译： 由钛和钨的合金的第一导体和诸如钼的难熔金属的第二导体组成的导电构件被烧结到具有低电阻率的硅的导电构件以与其形成低电阻接触。

公开(公告)号：US4522681A

公开(公告)日：1985-06-11

申请号：US602873

申请日：1984-04-23

申请人： Bernard Gorowitz ,  Richard J. Saia

发明人： Bernard Gorowitz ,  Richard J. Saia

IPC分类号： H01L21/302 ,  G03F7/09 ,  H01L21/3065 ,  H01L21/311 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/31116 ,  G03F7/094 ,  H01L21/31144

摘要： Holes in substrates are produced by a photolithography-plasma dry etching method employing a positive photoresist mask such as poly(methyl methacrylate) which is capable of being isotropically eroded by plasma action. The result is simultaneous anisotropic etching of the substrate and isotropic erosion of the mask, producing tapered holes.

摘要翻译： 通过使用能够通过等离子体作用各向同性地侵蚀的聚（甲基丙烯酸甲酯）等正性光致抗蚀剂掩模的光刻等离子体干蚀刻方法来制造衬底中的孔。 结果是基板的同时各向异性蚀刻和掩模的各向同性腐蚀，产生锥形孔。

公开(公告)号：US07011983B2

公开(公告)日：2006-03-14

申请号：US10324417

申请日：2002-12-20

申请人： Donald F. Foust ,  Anil R. Duggal ,  Richard J. Saia ,  Herbert S. Cole

发明人： Donald F. Foust ,  Anil R. Duggal ,  Richard J. Saia ,  Herbert S. Cole

IPC分类号： H01L51/40

CPC分类号： H01L51/0097 ,  H01L51/5036 ,  H01L51/52 ,  H01L51/5203 ,  H01L51/5212 ,  H01L51/524 ,  H01L51/5256 ,  H01L2251/5338 ,  H01L2251/5361 ,  Y02E10/549 ,  Y02P70/521

摘要： Large, light-weight organic devices and methods of preparing large, light-weight organic devices. Specifically, flexible and rigid light-weight plastics are implemented. The flexible plastic may be disposed from a reel. A metal grid is fabricated on the flexible plastic to provide current conduction over the large area. A transparent oxide layer is provided over the metal grid to form the bottom electrode of the organic device. A light emitting or light gathering organic layer is disposed on the transparent oxide layer. A second electrode is disposed over the organic layer. Electrodes are coupled to the metal grid and the second electrode to provide electrical current to or from the organic layer. Depending on the type of materials used for the organic layer, the organic device may comprise an area light device or a photovoltaic device.

摘要翻译： 大型，重量轻的有机器件和制备大型轻质有机器件的方法。 具体来说，实现了柔性和刚性轻质塑料。 柔性塑料可以从卷轴设置。 在柔性塑料上制造金属网格以在大面积上提供电流传导。 在金属网格上设置透明氧化物层以形成有机器件的底部电极。 发光或聚光有机层设置在透明氧化物层上。 第二电极设置在有机层上。 电极耦合到金属网格和第二电极以向有机层提供电流或从有机层提供电流。 根据用于有机层的材料的类型，有机器件可以包括区域光器件或光伏器件。

公开(公告)号：US5454904A

公开(公告)日：1995-10-03

申请号：US286722

申请日：1994-08-05

申请人： Mario Ghezzo ,  Richard J. Saia ,  Bharat S. Bagepalli ,  Imdad Imam ,  Dennis L. Polla

发明人： Mario Ghezzo ,  Richard J. Saia ,  Bharat S. Bagepalli ,  Imdad Imam ,  Dennis L. Polla

IPC分类号： B29C35/08 ,  B29C59/16 ,  H01H1/06 ,  H01H9/40 ,  H01H50/00 ,  B44C1/22 ,  B29C37/00 ,  C23F1/00

CPC分类号： H01H50/005 ,  B29C59/16 ,  B29C2035/0838 ,  H01H1/06 ,  H01H2001/0057 ,  H01H9/40 ,  Y10S438/94 ,  Y10T307/74

摘要： Micromachining methods for fabricating micromechanical structures which include plunger elements free to reciprocate within cavities are fabricated using processing steps in common with those employed in high density interconnect (HDI) technology for multi-chip module packaging. A polymer, such as a polyimide, is utilized as a micromachinable material. In one embodiment, cavities are formed in the polymer material by laser ablation, employing a sacrificial layer as a mask. Electroplated copper may be employed as a sacrificial release layer. One particular structure is a micromechanical electric switch including an array of individual switch contacts actuatable in common.

摘要翻译： 用于制造微机械结构的微加工方法，其包括在空腔内自由往复运动的柱塞元件的微机械结构使用与用于多芯片模块封装的高密度互连（HDI）技术中采用的步骤相同的处理步骤来制造。 聚合物如聚酰亚胺被用作可微加工材料。 在一个实施例中，通过激光烧蚀在聚合物材料中形成空腔，采用牺牲层作为掩模。 电镀铜可以用作牺牲剥离层。 一个特定结构是微机电式电开关，其包括可共同致动的单独开关触点的阵列。

公开(公告)号：US5362660A

公开(公告)日：1994-11-08

申请号：US977967

申请日：1992-11-18

申请人： Robert F. Kwasnick ,  George E. Possin ,  David E. Holden ,  Richard J. Saia

发明人： Robert F. Kwasnick ,  George E. Possin ,  David E. Holden ,  Richard J. Saia

IPC分类号： H01L21/3213 ,  H01L21/336 ,  H01L29/45 ,  H01L21/265

CPC分类号： H01L29/66765 ,  H01L21/32139 ,  H01L29/458 ,  Y10S438/97

摘要： Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

摘要翻译： 通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化，薄膜晶体管中的最小线间距减小，并且线间隔均匀性增加。 第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体，由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。 该蚀刻优选使用干蚀刻进行。 干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。 第二导体的蚀刻可以通过干法蚀刻工艺进行，该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂，由此第二导体设置有大致为45°的侧壁斜率，这提高了后续提供的钝化质量 共形钝化层的沉积。

公开(公告)号：US07158383B2

公开(公告)日：2007-01-02

申请号：US10716143

申请日：2003-11-18

申请人： Kevin M. Durocher ,  Richard J. Saia ,  Vikram B. Krishnamurthy

发明人： Kevin M. Durocher ,  Richard J. Saia ,  Vikram B. Krishnamurthy

IPC分类号： H05K1/16

CPC分类号： H01C17/12 ,  B29C59/14 ,  H01C7/006 ,  H05K1/0346 ,  H05K1/167 ,  H05K3/381 ,  H05K3/388 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2203/095 ,  H05K2203/1136

摘要： A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

摘要翻译： 一种在柔性基板上制造电阻器的技术。 具体地，通过暴露于离子溅射蚀刻技术来活化聚酰亚胺基底的至少一部分。 金属层设置在基板的激活部分上，从而形成高电阻金属碳化物区域。 互连层设置在金属碳化物区域上并被图案化以在金属碳化物区域的相对端形成端子。 将金属碳化物区域图案化以在端子之间形成电阻器。 或者，仅激活聚酰亚胺基板的选定区域。 所选择的区域形成形成金属碳化物区域的区域。 互连层设置在金属碳化物区域上并被图案化以在金属碳化物区域的相对端形成端子。