-
公开(公告)号：US20110095435A1
公开(公告)日：2011-04-28
申请号：US12607098
申请日：2009-10-28
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.
摘要翻译： 硅通孔（TSV）结构在硅衬底内形成独特的同轴或三轴互连。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。 还描述了制造这种TSV结构的方法。
-
公开(公告)号：US08242604B2
公开(公告)日：2012-08-14
申请号：US12607098
申请日：2009-10-28
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.
摘要翻译： 硅通孔（TSV）结构在硅衬底内形成独特的同轴或三轴互连。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。 还描述了制造这种TSV结构的方法。
-
公开(公告)号：US08394715B2
公开(公告)日：2013-03-12
申请号：US13495092
申请日：2012-06-13
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.
摘要翻译： 一种制造在硅衬底内形成独特的同轴或三轴互连的穿硅通孔（TSV）结构的方法。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。
-
公开(公告)号：US20120258589A1
公开(公告)日：2012-10-11
申请号：US13495092
申请日：2012-06-13
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.
摘要翻译： 一种制造在硅衬底内形成独特的同轴或三轴互连的穿硅通孔（TSV）结构的方法。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。
-
公开(公告)号：US06203690B1
公开(公告)日：2001-03-20
申请号：US09163148
申请日：1998-09-29
IPC分类号： C25F300
CPC分类号： H01L23/49811 , C25F3/02 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A process for reworking of PGA chip carriers where one or more I/O pins is unplated. The process includes electrolytically etching the I/O pins which removes any corrosion product from the unplated I/O pins and removes the top gold layer from the remaining I/O pins. The etchant includes a metal-providing compound selected from the group consisting of a silver salt, copper cyanide, silver cyanide, gold cyanide or mixtures thereof, at a concentration in the range from about 2.7 to about 4.1 g/l as metal; potassium or sodium carbonate at a concentration in the range from about 10 to about 100 g/l; and potassium or sodium cyanide at a concentration in the range from about 29 to about 35 g/l.
摘要翻译： 一种用于重新编码一个或多个I / O引脚未被放置的PGA芯片载体的过程。 该过程包括对I / O引脚进行电解蚀刻，从而从未镀覆的I / O引脚中除去任何腐蚀产物，并从剩余的I / O引脚中除去顶部金层。 蚀刻剂包括浓度为约2.7至约4.1g / l的金属的选自银盐，氰化铜，氰化银，氰化金或其混合物的金属提供化合物; 浓度在约10至约100g / l范围内的碳酸钾或碳酸钠; 和浓度在约29至约35g / l范围内的氰化钾或氰化钠。
-
公开(公告)号：US20090101626A1
公开(公告)日：2009-04-23
申请号：US11875227
申请日：2007-10-19
IPC分类号： B44C1/22
CPC分类号： H01L21/31111 , C09K13/04 , Y10T137/0318
摘要： An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first echant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.
摘要翻译： 蚀刻方法。 该方法包括在第一附魔中蚀刻第一多个硅晶片，每个硅晶片上沉积有SiO 2和Si 3 N 4，其中蚀刻包括将一定数量的SiO 2和一定量的Si 3 N 4溶解在第一吸附物中。 一定量的不溶性SiO2沉淀。 将Si 3 N 4的第一蚀刻速率与SiO 2的第一蚀刻速率的比率确定为小于预定阈值。 第一蚀刻剂的一部分与第二蚀刻剂组合以形成条件蚀刻剂。 在经调理的蚀刻剂中蚀刻第二多个硅晶片。 在条件化蚀刻剂中，Si 3 N 4的第二蚀刻速率与SiO 2的第二蚀刻速率之比大于阈值。 还公开了一种用于更换蚀刻浴溶液的方法和形成选择性蚀刻剂的方法。
-
公开(公告)号：US08298435B2
公开(公告)日：2012-10-30
申请号：US11875227
申请日：2007-10-19
IPC分类号： C03C25/68
CPC分类号： H01L21/31111 , C09K13/04 , Y10T137/0318
摘要： An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first echant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.
摘要翻译： 蚀刻方法。 该方法包括在第一附魔中蚀刻第一多个硅晶片，每个硅晶片上沉积有SiO 2和Si 3 N 4，其中蚀刻包括将一定数量的SiO 2和一定量的Si 3 N 4溶解在第一吸附物中。 一定量的不溶性SiO2沉淀。 将Si 3 N 4的第一蚀刻速率与SiO 2的第一蚀刻速率的比率确定为小于预定阈值。 第一蚀刻剂的一部分与第二蚀刻剂组合以形成条件蚀刻剂。 在经调理的蚀刻剂中蚀刻第二多个硅晶片。 在条件化蚀刻剂中，Si 3 N 4的第二蚀刻速率与SiO 2的第二蚀刻速率之比大于阈值。 还公开了一种用于更换蚀刻浴溶液的方法和形成选择性蚀刻剂的方法。
-
8.发明授权Apparatus for providing solder interconnections to semiconductor and electronic packaging devices 失效用于向半导体和电子封装装置提供焊料互连的装置
公开(公告)号：US6099935A
公开(公告)日：2000-08-08
申请号：US573469
申请日：1995-12-15
申请人： William Brearley , Laertis Economikos , Paul F. Findeis , Kimberley A. Kelly , Bouwe W. Leenstra , Arthur Gilman Merryman , Eric Daniel Perfecto , Chandrika Prasad , James Patrick Wood , Roy Yu
发明人： William Brearley , Laertis Economikos , Paul F. Findeis , Kimberley A. Kelly , Bouwe W. Leenstra , Arthur Gilman Merryman , Eric Daniel Perfecto , Chandrika Prasad , James Patrick Wood , Roy Yu
CPC分类号： H01L24/81 , H01L21/6835 , H01L24/75 , H05K3/3484 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/0568 , H01L2224/05684 , H01L2224/11003 , H01L2224/11332 , H01L2224/11334 , H01L2224/11472 , H01L2224/13111 , H01L2224/16 , H01L2224/742 , H01L2224/75 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15787 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/043 , Y10T428/24174 , Y10T428/24273 , Y10T428/24479
摘要： An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position. The depth is appropriate to facilitate wettingly attracting the solder material to the facing IO land when the apparatus is in the manufacturing position and the semiconductor device and the apparatus are exposed to appropriate ambient conditions to effect reflow of the solder material. The invention also includes a method for using the apparatus in manufacturing a semiconductor device.
摘要翻译： 一种用于制造半导体器件的装置，其具有以IO阵列布置在IO面上的输入 - 输出（IO）焊盘，该主体具有从操作面延伸到主体中的多个空腔; 空腔被布置在空腔轨迹阵列中，当该设备处于制造位置时，其中操作面大体上邻近IO面，该腔轨迹阵列与IO凸台对齐。 每个空腔具有深度和横向宽度，其协作以建立由空腔底部和至少一个空腔壁限定的体积。 当装置处于制造位置时，体积容纳适当量的焊料材料以建立在面对的IO焊盘上的焊料材料的量度。 当装置处于制造位置时，该深度适于促进将焊料材料润湿地吸引到相对的IO焊盘，并且半导体器件和设备暴露于适当的环境条件以实现焊料材料的回流。 本发明还包括一种在制造半导体器件中使用该装置的方法。
-
公开(公告)号：US09177822B2
公开(公告)日：2015-11-03
申请号：US13615770
申请日：2012-09-14
IPC分类号： B44C1/22 , C03C25/68 , H01L21/311 , C09K13/04
CPC分类号： H01L21/31111 , C09K13/04 , Y10T137/0318
摘要： An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first etchant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.
摘要翻译： 蚀刻方法。 该方法包括在第一附魔中蚀刻第一多个硅晶片，每个硅晶片上沉积有SiO 2和Si 3 N 4，其中蚀刻包括将一定量的SiO 2和一定量的Si 3 N 4溶解在第一蚀刻剂中。 一定量的不溶性SiO2沉淀。 将Si 3 N 4的第一蚀刻速率与SiO 2的第一蚀刻速率的比率确定为小于预定阈值。 第一蚀刻剂的一部分与第二蚀刻剂组合以形成条件蚀刻剂。 在经调理的蚀刻剂中蚀刻第二多个硅晶片。 在条件化蚀刻剂中，Si 3 N 4的第二蚀刻速率与SiO 2的第二蚀刻速率之比大于阈值。 还公开了一种用于更换蚀刻浴溶液的方法和形成选择性蚀刻剂的方法。
-
公开(公告)号：US20130011936A1
公开(公告)日：2013-01-10
申请号：US13615770
申请日：2012-09-14
CPC分类号： H01L21/31111 , C09K13/04 , Y10T137/0318
摘要： An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO2 and Si3N4 deposited thereon, where the etching includes dissolving a quantity of the SiO2 and a quantity of the Si3N4 in the first etchant. A quantity of insoluble SiO2 precipitates. A ratio of a first etch rate of Si3N4 to a first etch rate of SiO2 is determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of Si3N4 to a second etch rate of SiO2 in the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.
摘要翻译： 蚀刻方法。 该方法包括在第一附魔中蚀刻第一多个硅晶片，每个硅晶片上沉积有SiO 2和Si 3 N 4，其中蚀刻包括将一定量的SiO 2和一定量的Si 3 N 4溶解在第一蚀刻剂中。 一定量的不溶性SiO2沉淀。 将Si 3 N 4的第一蚀刻速率与SiO 2的第一蚀刻速率的比率确定为小于预定阈值。 第一蚀刻剂的一部分与第二蚀刻剂组合以形成条件蚀刻剂。 在经调理的蚀刻剂中蚀刻第二多个硅晶片。 在条件化蚀刻剂中，Si 3 N 4的第二蚀刻速率与SiO 2的第二蚀刻速率之比大于阈值。 还公开了一种用于更换蚀刻浴溶液的方法和形成选择性蚀刻剂的方法。
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.021 秒)
