公开(公告)号：US20080160256A1

公开(公告)日：2008-07-03

申请号：US11618752

申请日：2006-12-30

申请人： Robert L. Bristol ,  Chris E. Barns

发明人： Robert L. Bristol ,  Chris E. Barns

IPC分类号： G03F7/26 ,  B32B1/00

CPC分类号： H01L21/32139 ,  B24B37/042 ,  B24B37/24 ,  H01L21/02071 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/28123 ,  Y10T428/24372

摘要： The present invention describes a method including: providing a wafer; applying a photoresist over the wafer; forming a first set of features in the photoresist; etching a hard mask below the photoresist to form a second set of features in the hard mask; removing the photoresist; etching a polysilicon below the hardmask to form a third set of features in the polysilicon; removing the hard mask; and reducing a line edge roughness in the third set of features.

摘要翻译： 本发明描述了一种方法，包括：提供晶片; 在晶片上施加光致抗蚀剂; 在光致抗蚀剂中形成第一组特征; 蚀刻光致抗蚀剂下方的硬掩模以在硬掩模中形成第二组特征; 去除光致抗蚀剂; 在硬掩模之下蚀刻多晶硅以在多晶硅中形成第三组特征; 去除硬面膜; 并减少第三组特征中的线边缘粗糙度。

公开(公告)号：US07422936B2

公开(公告)日：2008-09-09

申请号：US10925517

申请日：2004-08-25

申请人： Chris E. Barns ,  Matt Prince ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros

发明人： Chris E. Barns ,  Matt Prince ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/78

摘要： Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.

摘要翻译： 可以通过从栅极结构去除多晶硅层来形成替代金属栅极。 栅极结构可以通过图案化多晶硅层并在栅极结构上沉积间隔层形成，使得间隔层具有第一抛光速率。 然后对间隔层进行蚀刻以形成侧壁间隔物。 在栅极结构上用侧壁间隔物施加层间电介质。 层间电介质具有比第一抛光速率高的第二抛光速率。 硬掩模也可以施加在栅极结构上并被植入，使得硬掩模可以更容易地去除。

公开(公告)号：US20080124857A1

公开(公告)日：2008-05-29

申请号：US11556025

申请日：2006-11-02

申请人： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

发明人： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

IPC分类号： H01L21/77 ,  H01L21/762 ,  H01L21/04

CPC分类号： H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

摘要翻译： 对半导体装置及其形成方法进行说明。 半导体器件包括形成在衬底的第一部分上的金属NMOS栅极电极和形成在衬底的第二部分上的硅化物PMOS栅极电极。

公开(公告)号：US07316949B2

公开(公告)日：2008-01-08

申请号：US11248737

申请日：2005-10-11

申请人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

发明人： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

公开(公告)号：US07078282B2

公开(公告)日：2006-07-18

申请号：US10749196

申请日：2003-12-30

申请人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

发明人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/7842

摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

公开(公告)号：US06558562B2

公开(公告)日：2003-05-06

申请号：US09948836

申请日：2001-09-07

申请人： Daniel S. Mallery ,  Doug Kreager ,  Chris E. Barns

发明人： Daniel S. Mallery ,  Doug Kreager ,  Chris E. Barns

IPC分类号： B44C122

CPC分类号： H01L21/68707 ,  G11B23/00

摘要： A wafer handling wand allows the efficient loading and unloading of semiconductor wafers to and from a CMP apparatus. The wand includes identical work piece gripping, alignment, and loading/unloading mechanisms on the top and bottom sides. A processed wafer can be unloaded from the apparatus onto one side of the wand and an unprocessed wafer can be loaded into the apparatus from the second side. The gripping mechanism includes a support area and a spaced apart moveable gripping finger. Wafer loading is facilitated by a cam attached to the support area that rotates when the cam contacts the apparatus. Upon rotation, the cam provides a surface for directing the work piece into the apparatus. The surface of the cam also includes an alignment aid that can be brought into contact with a reference surface on the apparatus to insure proper alignment between the wand and the apparatus.

公开(公告)号：US07569443B2

公开(公告)日：2009-08-04

申请号：US11159430

申请日：2005-06-21

申请人： Jack Kavalieros ,  Annalisa Cappellani ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Chris E. Barns ,  Robert S. Chau

发明人： Jack Kavalieros ,  Annalisa Cappellani ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Chris E. Barns ,  Robert S. Chau

IPC分类号： H01L21/338

CPC分类号： H01L29/66636 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7834

摘要： A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.

摘要翻译： 互补金属氧化物半导体集成电路可以形成有使用替换金属栅极和升高源极漏极形成的PMOS器件。 凸起的源极漏极可以由掺杂p型的外延沉积的硅锗材料形成。 替代金属栅极工艺导致金属栅电极，并且可能包括去除氮化物蚀刻停止层。

公开(公告)号：US07355281B2

公开(公告)日：2008-04-08

申请号：US11393151

申请日：2006-03-29

申请人： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Uday Shah ,  Chris E. Barns ,  Matthew V. Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Uday Shah ,  Chris E. Barns ,  Matthew V. Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert S. Chau

IPC分类号： H01L29/40

CPC分类号： H01L21/82345 ,  H01L21/28229 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成第一介电层，然后在第一介电层内形成沟槽。 在衬底上形成第二电介质层之后，在第二介电层的第一部分上的沟槽内形成第一金属层。 然后在第一金属层上和第二介电层的第二部分上形成第二金属层。

公开(公告)号：US07166506B2

公开(公告)日：2007-01-23

申请号：US11015151

申请日：2004-12-17

申请人： Matthew J. Prince ,  Francis M. Tambwe ,  Chris E. Barns

发明人： Matthew J. Prince ,  Francis M. Tambwe ,  Chris E. Barns

IPC分类号： H01L21/8242

CPC分类号： H01L21/31053 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.

摘要翻译： 公开了一种使用至少两种材料去除步骤制造微电子结构的方法，例如在多孔开式抛光工艺中。 在一个实施例中，第一去除步骤可以是利用相对于邻接晶体管栅极的蚀刻停止层使用的层间介电层具有高选择性的浆料的化学机械抛光（CMP）步骤。 这允许第一CMP步骤在接触蚀刻停止层之后停止，这导致基本上均匀的“在晶片内”，“在晶片内”和“晶片到晶片”形态。 去除步骤可以暴露诸如晶体管栅极结构内的多晶硅栅极的临时元件。 一旦多晶硅栅极被暴露，可以采用其它工艺来产生具有期望特性的晶体管栅极。

公开(公告)号：US07157378B2

公开(公告)日：2007-01-02

申请号：US10885958

申请日：2004-07-06

申请人： Justin K. Brask ,  Chris E. Barns ,  Mark L. Doczy ,  Uday Shah ,  Jack Kavalieros ,  Matthew V. Metz ,  Suman Datta ,  Anne E. Miller ,  Robert S. Chau

发明人： Justin K. Brask ,  Chris E. Barns ,  Mark L. Doczy ,  Uday Shah ,  Jack Kavalieros ,  Matthew V. Metz ,  Suman Datta ,  Anne E. Miller ,  Robert S. Chau

IPC分类号： H01L21/302

CPC分类号： H01L29/66545 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成电介质层，在电介质层内形成沟槽，并在沟槽内形成高k栅介质层。 在高k栅介质层上形成第一金属层之后，在第一金属层上形成第二金属层。 使用抛光步骤从电介质层上方去除第二金属层的至少一部分，并且使用蚀刻步骤从电介质层上方除去附加材料。