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公开(公告)号：US07723008B2
公开(公告)日：2010-05-25
申请号：US11087181
申请日：2005-03-22
IPC分类号： G03C1/00
CPC分类号： G03F7/091 , G03F7/0045
摘要： A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.
摘要翻译： 有助于减少半导体工艺效应的半导体工艺技术，例如不期望的线边缘粗糙度，光刻分辨率不足以及与去除光致抗蚀剂层相关的有限的焦深问题。 更具体地，本发明的实施例使用光致酸产生剂（PAG）材料结合牺牲光吸收材料（SLAM）来帮助减少在半导体制造过程中与去除光致抗蚀剂有关的这些和其它不期望的影响。 此外，本发明的实施例允许PAG以有效的方式应用于半导体制造过程中，与典型的现有技术相比需要较少的处理操作。
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公开(公告)号：US07718528B2
公开(公告)日：2010-05-18
申请号：US11620516
申请日：2007-01-05
IPC分类号： H01L21/302
CPC分类号： G03F7/091 , G03F7/0045
摘要： A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.
摘要翻译： 有助于减少半导体工艺效应的半导体工艺技术，例如不期望的线边缘粗糙度，光刻分辨率不足以及与去除光致抗蚀剂层相关的有限的焦深问题。 更具体地，本发明的实施例使用光致酸产生剂（PAG）材料结合牺牲光吸收材料（SLAM）来帮助减少在半导体制造过程中与去除光致抗蚀剂有关的这些和其它不期望的影响。 此外，本发明的实施例允许PAG以有效的方式应用于半导体制造过程中，与典型的现有技术相比需要较少的处理操作。
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公开(公告)号：US08513111B2
公开(公告)日：2013-08-20
申请号：US11485078
申请日：2006-07-12
申请人： Robert P. Meagley , Kevin P. O'Brien , Tian-An Chen , Michael D. Goodner , James Powers , Huey-Chiang Liou
发明人： Robert P. Meagley , Kevin P. O'Brien , Tian-An Chen , Michael D. Goodner , James Powers , Huey-Chiang Liou
IPC分类号： H01L23/58
CPC分类号： H01L23/5222 , H01L21/02118 , H01L21/02134 , H01L21/02137 , H01L21/02164 , H01L21/0234 , H01L21/02351 , H01L21/312 , H01L21/76224 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure may be covered with a thermally decomposing film. That film may then be covered by a sealing cover. Subsequently, the thermally decomposing material may be decomposed, forming a cavity.
摘要翻译： 半导体结构可以被热分解膜覆盖。 然后该膜可以被密封盖覆盖。 随后，热分解材料可能被分解，形成空腔。
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公开(公告)号：US07101798B2
公开(公告)日：2006-09-05
申请号：US10715956
申请日：2003-11-17
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76802
摘要： Several techniques are described for modulating the etch rate of a sacrificial light absorbing material (SLAM) by altering its composition so that it matches the etch rate of a surrounding dielectric. This is particularly useful in a dual damascene process where the SLAM fills a via opening and is etched along with a surrounding dielectric material to form trenches overlying the via opening.
摘要翻译： 描述了几种用于通过改变其组成以使其与周围电介质的蚀刻速率相匹配来调节牺牲光吸收材料（SLAM）的蚀刻速率的技术。 这在双镶嵌工艺中特别有用，其中SLAM填充通孔开口并与周围的电介质材料一起蚀刻以形成覆盖通孔开口的沟槽。
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公开(公告)号：US07572732B2
公开(公告)日：2009-08-11
申请号：US11417615
申请日：2006-05-03
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76802
摘要： Several techniques are described for modulating the etch rate of a sacrificial light absorbing material (SLAM) by altering its composition so that it matches the etch rate of a surrounding dielectric. This particularly useful in a dual damascene process where the SLAM fills a via opening and is etched along with a surrounding dielectric material to form trenches overlying the via opening.
摘要翻译： 描述了几种用于通过改变其组成以使其与周围电介质的蚀刻速率相匹配来调节牺牲光吸收材料（SLAM）的蚀刻速率的技术。 这在双镶嵌工艺中特别有用，其中SLAM填充通孔开口并与周围的电介质材料一起蚀刻以形成覆盖通孔开口的沟槽。
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公开(公告)号：US07344972B2
公开(公告)日：2008-03-18
申请号：US10829592
申请日：2004-04-21
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76825 , H01L21/76831
摘要： The invention provides a layer of photosensitive material that may be directly patterned. The photosensitive material may then be decomposed to leave voids or air gaps in the layer. This may provide a low dielectric constant layer with reduced resistance capacitance delay characteristics.
摘要翻译： 本发明提供可以直接图案化的感光材料层。 然后可以将感光材料分解以留下该层中的空隙或气隙。 这可以提供具有降低的电阻电容延迟特性的低介电常数层。
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公开(公告)号：US06833320B2
公开(公告)日：2004-12-21
申请号：US10287369
申请日：2002-11-04
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A thermally decomposable sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The thermally decomposable sacrificial material may be removed without damaging or removing the dielectric layer. The thermally decomposable sacrificial material may be a combination of organic and inorganic materials, such as a hydrocarbon-siloxane polymer hybrid.
摘要翻译： 将可热分解的牺牲材料沉积在半导体衬底上的电介质层的空隙或开口中。 可以除去可热分解的牺牲材料而不损坏或去除介电层。 可热分解的牺牲材料可以是有机和无机材料的组合，例如烃 - 硅氧烷聚合物杂化物。
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公开(公告)号：US20170053977A1
公开(公告)日：2017-02-23
申请号：US15342872
申请日：2016-11-03
IPC分类号： H01L49/02 , H01L23/48 , H01L23/522
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。 例如，半导体管芯包括衬底。 集成电路设置在基板的有源表面上。 电感器耦合到集成电路。 电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。 绝缘层具有起伏的形貌。
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公开(公告)号：US20140084414A1
公开(公告)日：2014-03-27
申请号：US13629168
申请日：2012-09-27
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。 例如，半导体管芯包括衬底。 集成电路设置在基板的有源表面上。 电感器耦合到集成电路。 电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。 绝缘层具有起伏的形貌。
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公开(公告)号：US20110260319A1
公开(公告)日：2011-10-27
申请号：US13103267
申请日：2011-05-09
申请人： Shriram Ramanathan , Patrick Morrow , Scott List , Michael Y. Chan , Mauro J. Kobrinsky , Sarah E. Kim , Kevin P. O'Brien , Michael C. Harmes , Thomas Marieb
发明人： Shriram Ramanathan , Patrick Morrow , Scott List , Michael Y. Chan , Mauro J. Kobrinsky , Sarah E. Kim , Kevin P. O'Brien , Michael C. Harmes , Thomas Marieb
IPC分类号： H01L23/498
CPC分类号： H01L24/16 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13099 , H01L2224/13147 , H01L2224/81205 , H01L2224/81801 , H01L2224/8183 , H01L2224/81894 , H01L2224/81895 , H01L2224/9202 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/19041
摘要： Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
摘要翻译： 具有可靠接合和衬底保护的三维堆叠衬底布置。
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