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    TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT
    1.
    发明申请
    TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT 有权
    用于可编程集成电路的抗融合结构

    公开(公告)号：US20100230781A1

    公开(公告)日：2010-09-16

    申请号：US12537473

    申请日：2009-08-07

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L23/525 ,  H01L21/768

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.

    摘要翻译： 沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。 反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层 沟槽的侧壁。 电介质层设置在导电插塞和掺杂区域之间。 电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。 沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

    FINFET WITH TOP BODY CONTACT
    2.
    发明申请
    FINFET WITH TOP BODY CONTACT 失效
    FINFET与身体接触

    公开(公告)号：US20090001464A1

    公开(公告)日：2009-01-01

    申请号：US11769032

    申请日：2007-06-27

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman

    IPC分类号： H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855

    摘要： FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin.

    摘要翻译： FinFET在半导体鳍片的顶表面上设有主体接触。 顶部本体接触可以相对于半导体鳍片和源极和漏极区域自对准。 或者，源极和漏极区域可以形成为从半导体鳍片的顶表面凹陷。 主体或身体的延伸部可以在通道上方或者源极和漏极区域之上接触。 通过源极和漏极区域从半导体鳍片的顶表面的凹陷来避免源极和漏极与主体接触之间的电短路。

    TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE
    3.
    发明申请
    TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE 有权
    具有自对准门的隧道效应晶体管

    公开(公告)号：US20090026491A1

    公开(公告)日：2009-01-29

    申请号：US11828740

    申请日：2007-07-26

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman

    IPC分类号： H01L29/70 ,  H01L21/33

    CPC分类号： H01L29/7391 ,  H01L23/485 ,  H01L29/66356 ,  Y10S438/926 ,  Y10S438/979

    摘要： In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

    摘要翻译： 在一个实施例中，可以使用心轴和外部虚拟间隔件来形成第一导电类型区域。 去除心轴以形成其中形成第二导电类型区域的凹陷区域。 在另一个实施例中，心轴从浅沟槽隔离中移除以形成凹陷区域，其中形成内部虚拟间隔物。 第一导电类型区域和第二导电区域形成在凹陷区域的其余部分内。 进行退火，使得第一导电类型区域和第二导电类型区域通过扩散彼此邻接。 栅电极形成为与第一和第二导电区域之间的p-n结自对准。 由栅电极控制的可能是亚光刻的p-n结构成本发明的隧道效应晶体管。

    PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE
    4.
    发明申请
    PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE 有权
    可编程高K /金属栅存储器件

    公开(公告)号：US20120184073A1

    公开(公告)日：2012-07-19

    申请号：US13433423

    申请日：2012-03-29

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

    摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

    摘要翻译： 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

    POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC
    5.
    发明申请
    POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC 有权
    用于与金属栅和高K电介质集成的多晶硅电阻器和电子熔断器

    公开(公告)号：US20110215321A1

    公开(公告)日：2011-09-08

    申请号：US12719289

    申请日：2010-03-08

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

    IPC分类号： H01L29/12 ,  H01L21/02 ,  H01L21/768 ,  H01L29/86 ,  H01L23/525

    CPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L29/12 ,  H01L29/86 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.

    摘要翻译： 提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。 该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域， 掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。 在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。 在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

    SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE
    6.
    发明申请
    SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE 有权
    与高K /金属闸门兼容的低压电容器

    公开(公告)号：US20090242953A1

    公开(公告)日：2009-10-01

    申请号：US12059174

    申请日：2008-03-31

    申请人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

    发明人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

    IPC分类号： H01L27/108 ,  H01L21/8242 ,  G06F17/50

    CPC分类号： H01L27/0629

    摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

    摘要翻译： 通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。 第二极性可以与第一极性相反。 额外的植入物可以减少第二细胞中的ESR。

    DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
    9.
    发明申请
    DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 有权
    半导体绝缘体基板上的深度隔离结构和深度电容器

    公开(公告)号：US20130147007A1

    公开(公告)日：2013-06-13

    申请号：US13316104

    申请日：2011-12-09

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L29/06 ,  H01L21/02

    CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

    摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

    摘要翻译： 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。