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公开(公告)号：US4063117A
公开(公告)日：1977-12-13
申请号：US757710
申请日：1977-01-07
申请人： Ronald C. Laugesen , Ury Priel
发明人： Ronald C. Laugesen , Ury Priel
CPC分类号： H03K17/06
摘要： In order to increase the output current of an MOS transistor, its gate is provided with a switched capacitor drive. A tri-state inverter is used to drive the output transistor gate from an input source. A pair of delay elements are cascaded to drive one input of a NOR gate, the other input of which is fed an undelayed signal. The NOR gate is used to switch a capacitor that is also coupled to the output transistor gate. The juncture between the delays is coupled to the control electrode of the tri-state inverter. During the first delay interval, the capacitor and the output transistor gate electrode are charged. Then after the second delay interval, which is shorter than the first, the capacitor is discharged into the output transistor gate electrode which is thereby driven substantially in excess of the conventional drive level.
摘要翻译： 为了增加MOS晶体管的输出电流，其栅极设置有开关电容器驱动器。 三态反相器用于从输入源驱动输出晶体管栅极。 一对延迟元件级联以驱动或非门的一个输入，其另一个输入端被馈送未延迟的信号。 NOR门用于切换也耦合到输出晶体管栅极的电容器。 延迟之间的时刻与三态逆变器的控制电极耦合。 在第一延迟间隔期间，电容器和输出晶体管栅电极被充电。 然后在比第一延迟间隔短的第二延迟间隔之后，电容器被放电到输出晶体管栅电极中，从而驱动基本上超过常规驱动电平。
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公开(公告)号：US4718057A
公开(公告)日：1988-01-05
申请号：US771339
申请日：1985-08-30
CPC分类号： G06F15/7832 , H04M1/253 , H04Q1/4575 , H04Q11/0428 , H04Q2213/13034 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/1319 , H04Q2213/13216 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13396 , H04Q2213/13405
摘要： An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals. The design of the general-purpose DSP is readily expandible to accomodate additional circuit elements and/or more signals to be processed in parallel.
摘要翻译： 公开了一种全数字信号处理器（DSP），其对于接收和发送的信号以及其他功能执行脉冲编码调制（PCM）编码和解码（CODEC）滤波操作。 用户可以通过微处理器访问各种可编程寄存器，以指定由DSP执行程序所使用的参数。 提供两个19位宽的双向数据总线用于各种元件之间的时分多路复用通信，其中包括随机存取存储器（RAM），算术逻辑单元（ALU）以及与接收端模拟到 数字（A / D）转换器和发射侧数模（D / A）转换器。 编程逻辑阵列（PLA）执行控制ALU部分处理信号的微码。 可以在PLA的控制下进行各种其他操作，例如通信中常用的双音多频（DTMF）信号的产生。 DSP的架构提供了许多用户可访问的寄存器，用于存储在DTMEC信号生成中使用的参数和系数，在CODEC滤波以及信号的压缩和扩展中。 通用DSP的设计很容易扩展，以容纳并行处理的附加电路元件和/或更多信号。
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公开(公告)号：US4641247A
公开(公告)日：1987-02-03
申请号：US771387
申请日：1985-08-30
IPC分类号： G06F7/00 , G06F15/16 , G06F15/177 , G06F15/78 , G06F15/60
CPC分类号： G06F15/7832 , G06F15/7896
摘要： A monolithic integrated circuit chip preferably includes a pair of data busses capable of conducting in parallel the number of signals which can be processed simultaneously by the components on the chip. Signals on the busses are carried in a time-multiplexed manner, each bus having a predetermined number of time slots. Preferably, each component on the chip is connected to one or both of the busses and is assigned a particular time slot for the bus to which it is connected. The resulting chip is of a structured, rather than a custom, design. Accordingly, it can be readily expanded or contracted in the number of signals which can be simultaneously processed. The number of components which can be included on the chip is limited only by the number of time slots available on the bus to which it is connected. By providing two busses, such common circuit elements as two-input adder/subtractors can be readily accommodated by a chip designed according to the instant invention. The bit-slice organization of the chip significantly reduces the design effort of the components connected to a bus, since a one-bit slice is merely replicated for each conductor of the bus. Ease of expansion along this dimension is achieved at virtually no cost.
摘要翻译： 单片集成电路芯片优选地包括能够并行地传导可由芯片上的组件同时处理的信号数的一对数据总线。 总线上的信号以时间复用的方式进行，每个总线具有预定数量的时隙。 优选地，芯片上的每个组件连接到一个或两个总线，并且为其连接的总线分配特定的时隙。 所产生的芯片是结构化的而不是定制的设计。 因此，可以容易地以可以同时处理的信号的数量扩展或收缩。 可以包括在芯片上的组件的数量仅受到其连接到的总线上可用的时隙的数量的限制。 通过提供两个总线，可以通过根据本发明设计的芯片容易地容纳诸如双输入加法器/减法器的公共电路元件。 芯片的位片组织显着降低了连接到总线的组件的设计工作量，因为只对总线的每个导体复制一位片。 实际上没有任何成本可以实现沿这个维度的扩展。
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公开(公告)号：US4124808A
公开(公告)日：1978-11-07
申请号：US763380
申请日：1977-01-28
IPC分类号： H03K5/24 , H03K19/003 , H03K1/02 , H03K5/18
CPC分类号： H03K5/2481 , H03K19/00384
摘要： A comparator amplifier circuit is integrated in MOS form. A sense amplifier section is coupled to a buffer amplifier section to provide an output that changes sharply at a particular voltage input. A compensating amplifier section is coupled between the comparator amplifier and a node in the buffer amplifier so that the voltage sense is independent of integrated circuit manufacturing variables.
摘要翻译： 比较器放大器电路以MOS形式集成。 感测放大器部分耦合到缓冲放大器部分以提供在特定电压输入处急剧变化的输出。 补偿放大器部分耦合在比较器放大器和缓冲放大器中的节点之间，使得电压检测与集成电路制造变量无关。
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公开(公告)号：US4049979A
公开(公告)日：1977-09-20
申请号：US717428
申请日：1976-08-24
IPC分类号： H03K5/02 , H03K19/017 , H03K19/0185 , H03K19/094 , H03K17/10 , H03K4/58 , H03K17/28 , H03K19/40
CPC分类号： H03K19/018507 , H03K19/01714 , H03K19/09425 , H03K5/023
摘要： Plural bootstrap capacitors are coupled to an output stage of a MOSFET driver. A conventional bootstrap driver is preceded by one or more additional bootstrap stages. Each one includes a capacitor, a tri state inverter and a delay section. When the output stage is off all capacitors are discharged. To turn the output stage on, all capacitors, including the output gate capacitance, are charged in parallel. Then each capacitor in turn is caused to pump its charge into the gate of the output stage, with the last capacitor pumping the output stage gate voltage to a level well in excess of the applied power supply voltage.
摘要翻译： 多个自举电容器耦合到MOSFET驱动器的输出级。 传统的引导驱动程序之前是一个或多个额外的引导阶段。 每个包括电容器，三态反相器和延迟部分。 当输出级关闭时，所有电容都放电。 为了打开输出级，所有电容器（包括输出栅极电容）都是并联的。 然后使每个电容器依次将其电荷泵送到输出级的栅极，最后一个电容器将输出级栅极电压泵浦到超过所施加的电源电压的电平。
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公开(公告)号：US3995232A
公开(公告)日：1976-11-30
申请号：US573912
申请日：1975-05-02
申请人： Ronald C. Laugesen
发明人： Ronald C. Laugesen
CPC分类号： H03K3/354 , H03K3/3545 , H03K4/501
摘要： An integrated circuit oscillator includes a timing circuit and a bistable circuit for controlling the timing circuit. The timing circuit includes a capacitor and a pair of field effect transistors (FET), one of which is employed for charging the capacitor and the other of which is employed for discharging the capacitor. A first stage having a relatively low trip voltage is responsive to a low level of charge on the capacitor for actuating the bistable circuit to a first state and a second stage having a relatively high trip voltage is responsive to a high level of charge on the capacitor for actuating the bistable circuit to a second state. The charging and discharging FET's are rendered conductive in response to the first and second states, respectively, of the bistable circuit, such that the capacitor is both charged and discharged over relatively long time periods. A pair of clamping circuits connected to the charging and discharging FET's reduce frequency variations which would normally occur with variations in process parameters and variations in the voltage level of the power supply.
摘要翻译： 集成电路振荡器包括定时电路和用于控制定时电路的双稳态电路。 定时电路包括电容器和一对场效应晶体管（FET），其中一个用于对电容器充电，另一个用于放电电容器。 具有相对低的跳闸电压的第一级响应于电容器上的低电荷电平，以将双稳态电路致动到第一状态，并且具有相对高的跳闸电压的第二级响应电容器上的高电平 用于致动双稳态电路到第二状态。 充电和放电FET分别响应于双稳态电路的第一和第二状态而导通，使得电容器在相对长的时间段内被充电和放电。 连接到充电和放电FET的一对钳位电路降低了通常随着工艺参数的变化和电源电压电平的变化而发生的频率变化。
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公开(公告)号：US4048524A
公开(公告)日：1977-09-13
申请号：US679120
申请日：1976-04-21
IPC分类号： G01R19/165 , H03K19/017 , H03K5/153 , H03K3/295 , H03K3/353 , H03K17/30
CPC分类号： G01R19/16519 , H03K19/01721
摘要： In a MOS integrated circuit, a voltage level detecting and indicating circuit apparatus is provided. In the apparatus there is provided a MOS integrated circuit means responsive to a change in the magnitude of a voltage in the circuit. In the circuit means there is provided a first node at which occurs a first signal when the magnitude of the voltage is changed to a first predetermined magnitude, said occurrence of said first signal being independent of at least one of a plurality of process variables including threshold voltage, mobility, body effect factor and lateral diffusion within a predetermined range of magnitude of said variable, and a second node at which occurs a second signal when said magnitude of said voltage is changed to a second predetermined magnitude and a third signal when said magnitude of said voltage is changed to the third predetermined magnitude, said occurrence of said second and third signals being dependent on at least one of said plurality of process variables.
摘要翻译： 在MOS集成电路中，提供电压电平检测和指示电路装置。 在该装置中，提供了响应于电路中的电压的大小变化的MOS集成电路装置。 在电路装置中，提供了一个第一节点，当电压的大小被改变到第一预定量值时，该第一节点出现第一信号，所述第一信号的发生独立于多个过程变量中的至少一个，包括阈值 电压，移动性，身体效应因子和横向扩散在所述变量的预定范围内，以及当所述电压的所述幅度改变为第二预定幅度时发生第二信号的第二节点和当所述幅度 的所述电压被改变到第三预定量值，所述第二和第三信号的发生取决于所述多个过程变量中的至少一个。
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